Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: Ib361cdfa43fc1c88d97e346d41b1cbf211c045d9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: Ie3909ef51c28a24728752a08ddf96a48d87d3cd7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Adapt to use errata frame-work cpu macro helpers for Cortex-A12
aarch32 cpu.
Testing:
- Manual comparison of disassembly with and without the patch.
- Compile testing.
Change-Id: I9bad7f1e3d87419c0451b5d46edf0c406d31a84d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Adapt to use errata frame-work cpu macro helpers for following cpu's:
- Cortex-A7
- Cortex-A9
Testing:
- Manual comparison of disassembly with and without the patch.
- Compile testing.
Change-Id: I88eb90d7fd0e82fc4bfc9d1aee947f0c820e1222
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the TF-A it is already returning an error when there is any request
to access these APIs. So, just removing the unused code to avoid the
confusion around these APIs.
Also, there is no issue with the backward compatibility as these APIs
were never used since implemented. Hence no need to bump up the
version of the feature check API as well.
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad
Deprecate pack_realm build command for TFTF.
To build Realm payload tests use ENABLE_REALM_PAYLOAD_TESTS=1.
This new command line for TFTF is effective from SHA 9945bef6b
in tf-a-tests repo.
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: Iee9ac9b2b367aac50677fac95631e7e4818cdf3a
Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime autodetection.
In addition this moves the evaluation of IMX_BOOT_UART_BASE into the
makefile which removes the ugly conditional compilation as well.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I92c13607bf81c6267f4b6aee829d74902b7f72d2
* changes:
feat(rdn2): enable Neoverse N2 CPU error handling support
feat(sgi): firmware first error handling for Neoverse N2 CPU
feat(arm): enable FHI PPI interrupt to report CPU errors
RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1, L2 tag and data RAMs. This node captures the error information in
its error records and generates fault handling interrupt on error event.
This patch adds reference implementation to demonstrate firmware-first
error handling of 1-bit CE that occur on CPU. On error event the error
handler reads the error records and ELx context information and forwards
it to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I769550efee10b9a3d89056bca4bfeb2db4708998
To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framework is initialized, only primary core is up and hence core FHI PPI
interrupt is enabled only on primary core. This patch adds support to
configure and enable core FHI interrupt for all the secondary cores as
part of their boot sequence.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656
In ZynqMP, the function zynqmp_config_setup() is common between bl31
and bl32(TSP). This function initializes IPI configuration and
prints the chip idcode and revision on the console, which is already
done in bl31 and redundant in bl32(TSP).
Remove the legacy code, reading the chip idcode and
revision information through direct register read.
Change-Id: I5da8e75a597ac9c4e1b56346e065d29e2be8787f
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case of SPD=tspd build option.
For ZYNQMP_WDT_RESTART build option GICV2_G0_FOR_EL3 needs to be
enabled and thus for ZynqMP GICV2_G0_FOR_EL3 is set to 1 by default.
On GICv2, when GICV2_G0_FOR_EL3 is set to 1, Group 0 interrupts
target EL3. This allows GICv2 platforms to enable features requiring
EL3 interrupt type.
This also means that all GICv2 Group 0 interrupts are delivered
to EL3, and the Secure Payload interrupts needs to be synchronously
handed over to Secure EL1 for handling.
Change-Id: I7eb72c6588ab41730a74ece261050840646de037
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header file include order in assembly files. With the above fix,
improper header order in assembly files has been detected.
Reorder the header includes in assembly files as per the update
in tf-a-ci-scripts.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4a4f3c5bb73886dae234160b893470443f1424fc
In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
function name in the functional documentation comments is not updated.
Update the function and variable names as per the above commit.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b777c21fe3673d29f809bf923eba38749f2c024
* changes:
refactor(cpus): convert Cortex-A72 to use cpu helpers
refactor(cpus): convert the Cortex-A72 to use the errata framework
refactor(cpus): reorder Cortex-A72 errata by ascending order
On systems with SCP (running crust) scpi_system_reboot action
performs board-level (PMIC) reboot. This doesn't preserve RAM content
on A64 PinePhone at least.
warm/soft system reset without RAM reset is required to get
pstore (persistent storage) in RAM working with Linux kernel. That is
very useful for oops/panic logging for post mortem analysis.
scpi_system_reset action performs reset via SoC reset (using watchdog)
and RAM content is preserved in this case. Linux kernel detects
system_reset2 support and uses it for warm reset automatically.
Change-Id: I1c21aa8f27c8e0395e2326034788693b59b80bc4
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Building for release with all errata flags enabled and running
script in change 19136 to compare output of objdump for each errata.
* Testing via script was not complete, as it directed to verify the
check and the workaround functions of few erratas manually.
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Manual comparison of disassembly of both both files(bl31.elf)
ensured,the ported changes were identical and hence verified.
* Build for release with all errata flags enabled and run default tftf
tests.
CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp \
ARCH=aarch64 \
DEBUG=0 \
HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 \
CTX_INCLUDE_AARCH32_REGS=0 \
ERRATA_A72_859971=1 \
ERRATA_A72_1319367=1 \
WORKAROUND_CVE_2017_5715=1 \
WORKAROUND_CVE_2018_3639=1 \
WORKAROUND_CVE_2022_23960=1 \
BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
fip all -j12
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure that if Errata are applicable then the workaround
functions are entered precisely.
Change-Id: I8ee5288f395b0391a242506e7effdb65ab4c4de7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Adapt to use errata frame-work cpu macro helpers for following cpus:
- cortex-a520
- cortex-a720
- cortex-x4
- cortex-chaberton
- cortex-blackhawk
- Use sysreg_bit_set helper macro for enabling of any system register
bit field.
- Use errata_report_shim macro for reporting errata.
- Use cpu_reset_func_start/end helpers for adding cpu reset functions.
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with erratas and stepping through from ArmDS and running tftf.
Change-Id: I954fb603aa3746e02f2288656b98148d9cfd7843
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Adds a dummy implementation of the plat_mboot_measure_key() function for
QEMU platform.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I64c1c751348c04cd359c075fc15a0d180ff55918
Added details about the API that calculates the signer-ID and updated
console log details to provide signer-ID information for each image.
Change-Id: If637b3719418e9c0b8d2844c92bddbdfe454bfb8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Added dummy implementation of 'plat_mboot_measure_key'
function for IMX platform.
Change-Id: Ib41fd86a9da330f62561707bda7d16f2825c0a7f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Implemented 'plat_mboot_measure_key' platform function for TC platform
to measure and publicise the public key information via RSS.
Change-Id: I10d90e921b135e729d5450d5a7468d0598072e60
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Once the Public Key has been verified, call 'plat_mboot_measure_key'
to measure and publicise it.
Change-Id: I46ea71dcbba96db3706602ccd89f22596ae68416
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Implemented 'plat_mboot_measure_key' platform function for FVP platform
to measure and publish the public key information via RSS.
Change-Id: I0c9d6d6ac3650a939437e9331ed3c9246f242830
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Added public key-OID information in the RSS metadata structure.
Change-Id: I5ee5d41519980091296deaa1882fdfe9ae6766c0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Key-OIDs that authenticate BL31, BL31(SOC)-FW config, and HW config
images have been explicitly entered.
Implementations of signer-ID consume these entries.
Change-Id: I24c9085ed5f266af06d40fb73302e35d857a9d5b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Calculate a hash of the public key and put that into the signer-ID
field of the relevant RSS metadata. The signer-ID metadata is mandatory
in the Arm CCA attestation scheme.
Change-Id: Ic846d8bf882cfea8581d3523a3461c919462df30
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Created an explicit zero-OID which can be used for Subject
Public Key that do not have their own key identifier.
With this, all keys (including the subject public key) have
a proper key OID string so we don't need to make a special
case of null pointers when it comes to handling key OIDs.
Change-Id: Ice6923951699b6e253d7fd87e4c1b912470e0391
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Added details of 'plat_mboot_measure_key' function in the porting-guide.
Change-Id: Id62211abc0ba13a0f581dc8e24c7b367afe2dcf5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* changes:
refactor(cpus): convert the Cortex-x2 to use cpu helpers
refactor(cpus): convert the Cortex-x2 to use the errata framework
refactor(cpus): reorder Cortex-x2 errata by ascending order
refactor(cpus): convert the Cortex-A65AE to use the errata framework
refactor(cpus): convert the Cortex-A510 to use cpu helpers
refactor(cpus): convert the Cortex-A510 to use the errata framework
refactor(cpus): reorder Cortex-A510 errata by ascending order
chore(fvp): add Aarch32 Cortex-A53 to the build
refactor(cpus): add Cortex-A53 errata framework information
feat(cpus): add errata framework helpers
chore(brcm): include cpu_helpers.S for bl2 build
Add support for Morello I2S audio subsystem. This includes adding the
audio formatter and I2S transmitter nodes and gluing them together with
the hdmi codec using a simple sound card machine node.
Change-Id: I3de4b06ef965c8e0555d074118b944fe6b4b78bb
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Faiz Abbas <faiz.abbas@arm.com>
