Commit graph

13689 commits

Author SHA1 Message Date
Olivier Deprez
48856003bf docs: add a section for experimental build options
A number of features are marked experimental in the build system through
makefiles but there wasn't an explicit document to list them.
Added a dedicated experimental build options section and moved
existing experimental build option descriptions in this section.

Restoring the change from [1] removing the experimental flag on the EL3
SPMC (this has been lost in rebasing a later change).

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24713

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2c458c6857c347114b265404e8b9ede9ac588463
2023-11-16 10:43:04 +01:00
Manish Pandey
f15f360cfc Merge "refactor(qemu): change way how we enable cpu features" into integration 2023-11-14 22:45:04 +01:00
Marcin Juszkiewicz
a97f4665d1 refactor(qemu): change way how we enable cpu features
We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2

And then we have QEMU's hybrid: 'max' which has everything QEMU can
emulate.

TF-A for QEMU platforms was built for v8.5 architecture. But turned out
that 'max' has v8.7 flag now (HCX) which we need to have. And this
enabled set of mandatory features which made TF-A not-bootable on
v8.0/8.2 cpus.

So I decided to follow Arm FVP way and do build for v8.0 with set of
feature flags enabled. This way we have bare minimum to make v8.0 cpus
boot. And then all features from newer cores are enabled with runtime
check which makes them boot.

Tested with BSA/SBSA ACS and Debian Linux 6.5 kernel.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ib87bdab992536c65ce0747ce1520682eafc18d39
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2023-11-14 17:59:22 +02:00
Joanna Farley
d1cfbc25c5 Merge changes from topic "od/hf-doc-migration" into integration
* changes:
  docs(spm-mm): remove reference to SEL2 SPMC
  docs: remove SEL2 SPMC threat model
  docs: remove unused SPM related diagrams
2023-11-14 09:52:12 +01:00
Sandrine Bailleux
dcbf3a1173 Merge "docs(threat-model): cover threats inherent to receiving data over UART" into integration 2023-11-14 08:43:42 +01:00
Manish V Badarkhe
5e52433dd6 Merge "build(mbedtls): add deprecation notice" into integration 2023-11-13 20:01:39 +01:00
Manish V Badarkhe
24ef3a3146 Merge "refactor(auth): remove return_if_error() macro" into integration 2023-11-13 20:01:22 +01:00
Sandrine Bailleux
575c146962 refactor(auth): remove return_if_error() macro
The usage of this macro hinders the accuracy of code coverage
data. Lines of code calling this macro always appear as covered because
the test condition within it always gets executed; however, the branch
is not necessarily taken. Consequently, we lose branch coverage
information on these error code paths.

Besides, it is debatable whether such a simple macro really improves
code readability or on the contrary obfuscates the code...

For these reasons, this patch inlines the macro code everywhere it was
called.

It also adds some error messages in all these places to help narrowing
down authentication failures. These messages only get displayed and
compiled into the binaries when building TF-A with 'LOG_VERBOSE' level
of verbosity. We use the same message string everywhere in order to
limit the memory footprint increase for 'LOG_VERBOSE' builds.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I461078bb8c6fd6811d2cbefbe3614e17e83796f2
2023-11-13 16:07:21 +01:00
Govindraj Raja
267c106f02 build(mbedtls): add deprecation notice
Add a deprecation notice for building TF-A with mbedtls-2.x
This was notified earlier in TF-A mailing list:

https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/message/YDPOPASMGEQBCOI5TKUSD3V3J75NAT7A/

We will be removing support to build TF-A with mbedtls-2.x after
TF-A 2.10 release.

Change-Id: I669b423ee9af9f5c5255fce370413fffaf38e8eb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-11-13 08:49:58 -06:00
Sandrine Bailleux
348446ad2a docs(threat-model): cover threats inherent to receiving data over UART
TF-A supports reading input data from UART interfaces. This opens up
an attack vector for arbitrary data to be injected into TF-A, which is
not covered in the threat model right now.

Fill this gap by:

 - Updating the data flow diagrams. Data may flow from the UART into
   TF-A (and not only the other way around).

 - Documenting the threats inherent to reading untrusted data from a
   UART.

Change-Id: I508da5d2f7ad5d20717b958d76ab9337c5eca50f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2023-11-13 10:28:24 +01:00
Manish Pandey
e7781c84e9 Merge "fix(arm): correct the SPMC_AT_EL3 condition" into integration 2023-11-08 18:53:03 +01:00
Olivier Deprez
d910b37039 Merge "fix(xlat): set MAX_PHYS_ADDR to total mapped physical region" into integration 2023-11-08 16:35:18 +01:00
Manish Pandey
9c473d888a Merge "fix(intel): update boot scratch cold register to use cold 8" into integration 2023-11-08 15:52:18 +01:00
Manish Pandey
31a815db1a Merge changes from topic "sb/remove-cryptocell" into integration
* changes:
  chore(npcm845x): remove CryptoCell-712/713 support
  chore(auth)!: remove CryptoCell-712/713 support
2023-11-08 15:26:38 +01:00
Sandrine Bailleux
03baf340b2 Merge "docs(qemu): mention a55 in list of v8.2 cores" into integration 2023-11-08 14:54:14 +01:00
Sandrine Bailleux
7f26777702 Merge "build(qemu): use xlat tables v2 directly" into integration 2023-11-08 13:49:52 +01:00
Sandrine Bailleux
0c5aafc652 chore(npcm845x): remove CryptoCell-712/713 support
CryptoCell-712 and CryptoCell-713 drivers have been deprecated. Remove
their usage on Nuvoton npcm845x platform (maintainers confirmed that
this removal is fine with them).

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I0e3f3431558aaea1e0f2740e7088cdc155d06af2
2023-11-08 13:42:34 +01:00
Marcin Juszkiewicz
70524d3df6 build(qemu): use xlat tables v2 directly
Both qemu and qemu-sbsa use xlat tables v2 already (activated by including it 
in common/common.mk) so there is no need to include compat headers.

Change-Id: I353a6f77f5916862e54b883a9adbba027ac81359
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2023-11-08 13:22:06 +02:00
Marcin Juszkiewicz
c41b16eadb docs(qemu): mention a55 in list of v8.2 cores
Change-Id: Ib3a1711be323023cf111373111f39038fa23fb6f
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2023-11-08 11:54:42 +01:00
Manish V Badarkhe
a0ef1c0ef0 fix(arm): correct the SPMC_AT_EL3 condition
Addressed the SPMC_AT_EL3 condition by using '#if' instead of
'#if defined'. This change is warranted because the SPMC_AT_EL3
option is always defined.

Change-Id: I76d9b8d502f452c58bc0040745d642cbe11dc8eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-11-08 09:33:23 +00:00
Sandrine Bailleux
b65dfe40ae chore(auth)!: remove CryptoCell-712/713 support
CryptoCell-712 and CryptoCell-713 drivers have been deprecated since
TF-A v2.9 and their removal was announced for TF-A v2.10 release.
See [1].

As the release is approaching, this patch deletes these drivers' code as
well as all references to them in the documentation and Arm platforms
code (Nuvoton platform is taken care in a subsequent patch). Associated
build options (ARM_CRYPTOCELL_INTEG and PLAT_CRYPTOCELL_BASE) have also
been removed and thus will have no effect if defined.

This is a breaking change for downstream platforms which use these
drivers.

[1] https://trustedfirmware-a.readthedocs.io/en/v2.9/about/release-information.html#removal-of-deprecated-drivers
    Note that TF-A v3.0 release later got renumbered into v2.10.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Idabbc9115f6732ac1a0e52b273d3380677a39813
2023-11-08 10:42:33 +02:00
Sandrine Bailleux
dde37f2d76 Merge "build(qemu-sbsa): it is GICv3 platform" into integration 2023-11-08 08:14:26 +01:00
Manish Pandey
d4f5063337 Merge changes Ia72b2542,I1eba5671 into integration
* changes:
  chore(compiler-rt): update compiler-rt source files
  chore(zlib): update zlib to version 1.3
2023-11-07 17:56:50 +01:00
Manish Pandey
2f306f892e Merge "chore(libfdt): update header files to v1.7.0 tag" into integration 2023-11-07 17:25:56 +01:00
Manish Pandey
e5e39c3514 Merge "refactor(cm): introduce INIT_UNUSED_NS_EL2 macro" into integration 2023-11-07 17:24:56 +01:00
Olivier Deprez
5e86ba2138 Merge "fix(el3-spmc): remove experimental flag" into integration 2023-11-07 16:02:02 +01:00
Manish V Badarkhe
c1701c8ec9 Merge changes from topic "ns/spmc_at_el3" into integration
* changes:
  feat(sgi): increase sp memmap size
  feat(build): include plat header in fdt build
  feat(docs): save BL32 image base and size in entry point info
  feat(arm): save BL32 image base and size in entry point info
2023-11-07 15:47:44 +01:00
Olivier Deprez
e0c7d8f56c Merge "fix(smccc): ensure that mpidr passed through SMC is valid" into integration 2023-11-07 13:35:30 +01:00
Olivier Deprez
630a06c4c6 fix(el3-spmc): remove experimental flag
The EL3 SPMC is known to be deployed into end products and properly
tested since its introduction into TF-A v2.7.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I96bb897cfefef20c33cfc39627b10746dce5485c
2023-11-07 12:14:47 +01:00
Nishant Sharma
7c33bcab59 feat(sgi): increase sp memmap size
With FF-A enabled on SP at SEL0 enabled, SPMC at EL3 needs more entries
to map newly added regions(SP, Rx/Tx buffer and Manifest).

Increase the PLAT_SP_IMAGE_MMAP_REGIONS to 14 and MAX_XLAT_TABLES to 9.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I96fd291db8eb178f7aa73b5a9e38cfc67c66fa91
2023-11-07 10:36:53 +00:00
Nishant Sharma
e03dcc8f5e feat(build): include plat header in fdt build
Include platform headers in DT build to enable build time configuration
of number of execution context supported by the platform.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I5b9ffc9865f198a1f802fcb5e0950a5fabb48727
2023-11-07 10:36:53 +00:00
Nishant Sharma
31dcf23451 feat(docs): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I35527fb41829102083b488a5150c0c707c5ede15
2023-11-07 10:36:53 +00:00
Nishant Sharma
821b01fa75 feat(arm): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Id41cedd790ca1713787e5516fb84666d1ccb0b03
2023-11-07 10:36:53 +00:00
Arvind Ram Prakash
183329a584 refactor(cm): introduce INIT_UNUSED_NS_EL2 macro
Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL2. Platforms without NS-EL2 in use
must enable this flag.

BREAKING CHANGE: Initialisation code for handoff from EL3 to NS-EL1
disabled by default. Platforms which do that need to enable this macro
going forward

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I61431cc4f7e2feb568d472828e5fd79cc73e51f5
2023-11-06 22:57:16 +01:00
Manish Pandey
cdd6089db0 chore(compiler-rt): update compiler-rt source files
Update the compiler-rt source files to the tip of llvm-project [1].

[1] https://github.com/llvm/llvm-project/commit/ab97b89d03a7

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia72b25423896a530bf5bb68ff067184b2314e2be
2023-11-06 21:14:01 +00:00
Manish Pandey
fd39217a74 chore(zlib): update zlib to version 1.3
Update the zlib source files to the latest tagged version 1.3 [1].

[1] https://github.com/madler/zlib/tree/v1.3

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1eba5671efab75699e68fc2f2aa9400d0f5aba7d
2023-11-06 21:13:38 +00:00
Manish Pandey
d3a9990c6a chore(libfdt): update header files to v1.7.0 tag
As part of TF-A 2.9.0 release, libfdt version was updated to its last
tagged version (1.7.0) with commit 058e017e5. This commit has only
updated the source files of libfdt but did not update header files.

This patch updates the libfdt header files in include/lib/libfdt to
the tagged version v1.7.0

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I09a0f51435b343c3e1cac45075fe7d28cbcae867
2023-11-06 21:13:22 +00:00
Manish Pandey
e60c18471f fix(smccc): ensure that mpidr passed through SMC is valid
There are various SMC calls which pass mpidr as an argument which is
currently tested at random places in SMC call path.
To make the mpidr validation check consistent across SMC calls, do
this check as part of SMC argument validation.

This patch introduce a helper function is_valid_mpidr() to validate
mpidr and call it as part of validating SMC arguments at starting of
SMC handlers (which expect mpidr as an argument).

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I11ea50e22caf17896cf4b2059b87029b2ba136b1
2023-11-06 20:43:38 +00:00
Marcin Juszkiewicz
b54dfb5d33 build(qemu-sbsa): it is GICv3 platform
GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d816e6c60a344f895
2023-11-06 20:39:32 +02:00
Manish Pandey
5a4c3f0baa Merge "fix(sdei): ensure that interrupt ID is valid" into integration 2023-11-06 19:01:26 +01:00
Joanna Farley
1684c8d6a1 Merge changes from topic "enable_assertion" into integration
* changes:
  feat(zynqmp): enable assertion
  feat(versal-net): enable assertion
  feat(versal): enable assertion
2023-11-06 17:55:20 +01:00
Lauren Wehrmeister
11a8a3e935 Merge changes from topic "errata" into integration
* changes:
  fix(cpus): workaround for Cortex-X2 erratum 2742423
  fix(cpus): workaround for Cortex-A710 erratum 2742423
  fix(cpus): workaround for Neoverse N2 erratum 2340933
  fix(cpus): workaround for Neoverse N2 erratum 2346952
2023-11-06 17:33:30 +01:00
Madhukar Pappireddy
9ac3bcdd9a Merge "fix(ti): release lock in all TI-SCI xfer return paths" into integration 2023-11-06 15:50:27 +01:00
Joanna Farley
bfb8d8eba6 Merge "feat(xilinx): switch boot console to runtime" into integration 2023-11-06 14:55:07 +01:00
Olivier Deprez
29683ef78f Merge "docs: add TF-A version numbering information" into integration 2023-11-06 13:51:33 +01:00
Joanna Farley
d5fe7088ce Merge "feat(zynqmp): remove pm_ioctl_set_sgmii_mode api" into integration 2023-11-06 09:21:54 +01:00
Andrew Davis
e92375e07c fix(ti): release lock in all TI-SCI xfer return paths
Failing to send a message is often not fatal and we will end up trying
to send again. This would fail as some exit paths do not release the
secure proxy xfer lock. Release this lock on all return paths.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I3939015774f819572dbd26720b2c105fba7574cb
2023-11-03 14:46:47 -05:00
Manish V Badarkhe
9bb15ab53a Merge changes from topic "morello/firmware-revision" into integration
* changes:
  feat(morello): add TF-A version string to NT_FW_CONFIG
  feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version
2023-11-03 14:31:40 +01:00
Joanna Farley
dd532b9e1d Merge changes from topic "xlnx_tsp_feat" into integration
* changes:
  docs(versal-net): add TSP build documentation
  docs(versal): add TSP build documentation
  feat(versal-net): add tsp support
  feat(versal): add tsp support
  refactor(xilinx): add generic TSP makefile
  chore(zynqmp): reorganize tsp code into common path
  refactor(xilinx): rename platform function to generic name
2023-11-03 14:29:49 +01:00
Jit Loon Lim
655af4f492 fix(intel): update boot scratch cold register to use cold 8
Boot scratch cold 8 register is fully used by n5x.
Update to use boot scratch cold 8 bit 19 register for cpu0 ON/OFF
indicator.

Change-Id: I45ebfdcc17c47bcce69f5f611e677ac7838ecf52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
2023-11-03 20:03:45 +08:00