When fdt_add_reserved_memory() is called to add a memory region, we
unconditionally add a node for that region. However there might be an
existing region node in the DT already, or there might be an overlapping
region. The Linux kernel will complain in those cases.
Cover the simple case of the region already existing in the DT, as this
is what we actually see on the Allwinner H616: The mainline DT contains
a node reserving the memory for TF-A, in case the DT changed by TF-A
itself is not given to the kernel. Our code always adds a region, making
the kernel complain - albeit without further consequences.
Covering all cases of overlapping regions would blow up the generic DT
code too much, so just add a simple check for an existing region
completely containing the to-be-added region, simply bailing out in this
case.
This prevents the kernel warning for the Allwinner H616.
This code requires a function from fdt_wrappers.c, so we have to include
that file for platforms that use the fdt_add_reserved_memory() function
(rpi4 and versal2).
Change-Id: I98404889163316addbb42130d7177f1a21c8be06
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
BCM2712 changes:
- support all 3 PCIe RCs / segments.
- don't check for link up: the RC can now be configured to fabricate
all-ones AXI OKAY responses, so no more Arm SErrors when the link is
down (or other conditions).
Also, limit bus 0 to devfn 0 as accesses beyond that may result in
lock-ups.
Change-Id: Ic64785cd68b22571c6638fc3f771703113bc76f6
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
Detection of the UART in use and GPIO code only apply to RPi 3 and 4.
RPi 5 has a dedicated PL011 debug port.
Change-Id: Iddf8aea01278e2b79b4e7c476740f1add8c419f0
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
In preparation for RPi 5 support, which will reuse most of the RPi 4
logic except for DTB patching.
Change-Id: I6f6ef96933711a1798757a3389adae1b8ee3de6c
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
The toolchain refactor change introduces the `${toolchain}-${tool}-id`
variables, which provide identifiers for all of the toolchain tools used
by the build system. This change replaces the various conditions that
are in use to identify these tools based on the path with a standard set
of comparisons against these new identifier variables.
Change-Id: Ib60e592359fa6e415c19a012e68d660f87436ca7
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change migrates the values of `CC`, `CPP`, `AS` and other toolchain
variables to the new `$(toolchain)-$(tool)` variables, which were
introduced by the toolchain refactor patch. These variables should be
equivalent to the values that they're replacing.
Change-Id: I644fe4ce82ef1894bed129ddb4b6ab94fb04985d
Signed-off-by: Chris Kay <chris.kay@arm.com>
Now that we have adjusted the address map, added the
SMC conduit code, and the RPi4 PCI callbacks, lets
add the flags to enable everything in the build.
By default this service is disabled because the
expectation is that its only useful in a UEFI+ACPI
environment.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: I2a3cac6d63ba8119d3b711db121185816b89f8a2
Addresses the deprecation warning produced by
drivers/arm/gic/common/gic_common.c.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I1a3ff4835d0f94c74b405db10622e99875ded82b
The plat_helpers.S file was almost identical between its RPi3 and RPi4
versions. Unify the two files, moving it into the common/ directory.
This adds a plat_rpi_get_model() function, which can be used to trigger
RPi4 specific action, detected at runtime. We use that to do the RPi4
specific L2 cache initialisation.
Change-Id: I2295704fd6dde7c76fe83b6d98c7bf998d4bf074
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Raspberry Pi has two different UART devices pin-muxed to GPIO 14&15:
One ARM PL011 one and the 8250 compatible "Mini-UART".
A dtoverlay parameter in config.txt will tell the firmware to switch
between the two: it will setup the right clocks and will configure the
pinmuxes accordingly.
To autodetect the user's choice, we read the pinmux register and check
its setting: ALT5 (0x2) means the Mini-UART is used, ALT0 (0x4) points
to the PL011.
Based on that we select the UART driver to initialise.
This will allow console output in any case.
Change-Id: I620d3ce68de6c6576599f2a405636020e1fd1376
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Broadcom 283x SoCs feature multiple UARTs: the mostly used
"Mini-UART", which is an 8250 compatible IP, and at least one PL011.
While the 8250 is usually used for serial console purposes, it suffers
from a design flaw, where its clock depends on the VPU clock, which can
change at runtime. This will reliably mess up the baud rate.
To avoid this problem, people might choose to use the PL011 UART for
the serial console, which is pin-mux'ed to the very same GPIO pins.
This can be done by adding "miniuart-bt" to the "dtoverlay=" line in
config.txt.
To prepare for this situation, use the newly gained freedom of sharing
one console_t pointer across different UART drivers, to introduce the
option of choosing the PL011 for the console.
This is for now hard-coded to choose the Mini-UART by default.
A follow-up patch will introduce automatic detection.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05
The device tree provided by the official Raspberry Pi firmware uses
spin tables for SMP bringup.
One of the benefit of having TF-A is that it provides PSCI services, so
let's rewrite the DTB to advertise PSCI instead of spin tables.
This uses the (newly exported) routine from the QEMU platform port.
Change-Id: Ifddcb14041ca253a333f8c2d5e97a42db152470c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that we have the armstub magic value in place, the GPU firmware will
write the kernel load address (and DTB address) into our special page,
so we can always easily access the actual location without hardcoding
any addresses into the BL31 image.
Make the compile-time defined PRELOADED_BL33_BASE macro optional, and
read the BL33 entry point from the magic location, if the macro was not
defined. We do the same for the DTB address.
This also splits the currently "common" definition of
plat_get_ns_image_entrypoint() to be separate between RPi3 and RPi4.
Change-Id: I6f26c0adc6fce2df47786b271c490928b4529abb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Raspberry Pi GPU firmware checks for a magic value at offset 240
(0xf0) of the armstub8.bin image it loads. If that value matches,
it writes the kernel load address and the DTB address into subsequent
memory locations.
We can use these addresses to avoid hardcoding these values into the BL31
image, to make it more flexible and a drop-in replacement for the
official armstub8.bin.
Reserving just 16 bytes at offset 240 of the final image file is not easily
possible, though, as this location is in the middle of the generic BL31
entry point code.
However we can prepend an extra section before the actual BL31 image, to
contain the magic and addresses. This needs to be 4KB, because the
actual BL31 entry point needs to be page aligned.
Use the platform linker script hook that the generic code provides, to
add an almost empty 4KB code block before the entry point code. The very
first word contains a branch instruction to jump over this page, into
the actual entry code.
This also gives us plenty of room for the SMP pens later.
Change-Id: I38caa5e7195fa39cbef8600933a03d86f09263d6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Raspberry Pi 4 is a single board computer with four Cortex-A72
cores. From a TF-A perspective it is quite similar to the Raspberry Pi
3, although it comes with more memory (up to 4GB) and has a GIC.
This initial port though differs quite a lot from the existing rpi3
platform port, mainly due to taking a much simpler and more robust
approach to loading the non-secure payload:
The GPU firmware of the SoC, which is responsible for initial platform
setup (including DRAM initialisation), already loads the kernel, device
tree and the "armstub" into DRAM. We take advantage of this, by placing
just a BL31 component into the armstub8.bin component, which will be
executed first, in AArch64 EL3.
The non-secure payload can be a kernel or a boot loader (U-Boot or
EDK-2), disguised as the "kernel" image and loaded by the GPU firmware.
So this is just a BL31-only port, which directly drops into EL2
and executes whatever has been loaded as the "kernel" image, handing
over the DTB address in x0.
Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
