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f5cb15b0c8
The Raspberry Pi 4 is a single board computer with four Cortex-A72 cores. From a TF-A perspective it is quite similar to the Raspberry Pi 3, although it comes with more memory (up to 4GB) and has a GIC. This initial port though differs quite a lot from the existing rpi3 platform port, mainly due to taking a much simpler and more robust approach to loading the non-secure payload: The GPU firmware of the SoC, which is responsible for initial platform setup (including DRAM initialisation), already loads the kernel, device tree and the "armstub" into DRAM. We take advantage of this, by placing just a BL31 component into the armstub8.bin component, which will be executed first, in AArch64 EL3. The non-secure payload can be a kernel or a boot loader (U-Boot or EDK-2), disguised as the "kernel" image and loaded by the GPU firmware. So this is just a BL31-only port, which directly drops into EL2 and executes whatever has been loaded as the "kernel" image, handing over the DTB address in x0. Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
108 lines
2.8 KiB
Makefile
108 lines
2.8 KiB
Makefile
#
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# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/libfdt/libfdt.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_INCLUDES := -Iplat/rpi/common/include \
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-Iplat/rpi/rpi4/include
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PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
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plat/rpi/common/rpi3_common.c \
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${XLAT_TABLES_LIB_SRCS}
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BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \
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plat/rpi/rpi4/aarch64/plat_helpers.S \
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drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicv2_main.c \
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plat/common/plat_gicv2.c \
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plat/rpi/rpi4/rpi4_bl31_setup.c \
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plat/rpi/common/rpi3_pm.c \
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plat/common/plat_psci_common.c \
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plat/rpi/common/rpi3_topology.c \
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${LIBFDT_SRCS}
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# For now we only support BL31, using the kernel loaded by the GPU firmware.
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RESET_TO_BL31 := 1
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# All CPUs enter armstub8.bin.
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COLD_BOOT_SINGLE_CPU := 0
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# Tune compiler for Cortex-A72
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ifeq ($(notdir $(CC)),armclang)
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TF_CFLAGS_aarch64 += -mcpu=cortex-a72
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else ifneq ($(findstring clang,$(notdir $(CC))),)
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TF_CFLAGS_aarch64 += -mcpu=cortex-a72
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else
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TF_CFLAGS_aarch64 += -mtune=cortex-a72
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endif
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# Enable all errata workarounds for Cortex-A72
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ERRATA_A72_859971 := 1
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WORKAROUND_CVE_2017_5715 := 1
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# Add new default target when compiling this platform
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all: bl31
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# Build config flags
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# ------------------
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# Disable stack protector by default
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ENABLE_STACK_PROTECTOR := 0
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# Have different sections for code and rodata
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SEPARATE_CODE_AND_RODATA := 1
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# Use Coherent memory
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USE_COHERENT_MEM := 1
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# Platform build flags
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# --------------------
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# Assume that BL33 isn't the Linux kernel by default
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RPI3_DIRECT_LINUX_BOOT := 0
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# BL33 images are in AArch64 by default
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RPI3_BL33_IN_AARCH32 := 0
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# UART to use at runtime. -1 means the runtime UART is disabled.
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# Any other value means the default UART will be used.
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RPI3_RUNTIME_UART := 0
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# Use normal memory mapping for ROM, FIP, SRAM and DRAM
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RPI3_USE_UEFI_MAP := 0
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# Process platform flags
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# ----------------------
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$(eval $(call add_define,RPI3_BL33_IN_AARCH32))
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$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT))
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ifdef RPI3_PRELOADED_DTB_BASE
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$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE))
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endif
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$(eval $(call add_define,RPI3_RUNTIME_UART))
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$(eval $(call add_define,RPI3_USE_UEFI_MAP))
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# Verify build config
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# -------------------
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#
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ifneq (${RPI3_DIRECT_LINUX_BOOT}, 0)
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ifndef RPI3_PRELOADED_DTB_BASE
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$(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1)
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endif
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endif
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ifeq (${ARCH},aarch32)
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$(error Error: AArch32 not supported on rpi4)
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endif
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ifneq ($(ENABLE_STACK_PROTECTOR), 0)
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PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \
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plat/rpi/common/rpi3_stack_protector.c
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endif
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