When resume from APD sleep mode, need to add a small delay
before accessing the CMC1 register.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ic8acdf58a3bf82b1791e7ae7f173f8c94c56b49d
for some user case, the ddr may need to be controlled
by RTD side to save power, when APD resume from low
power mode, it should wait ddr is ready for access.
currently we use a GPR in SIM_RTD_SEC as a flag to
indicate when the DDR is for access, non-zero value
means the DDR can be access from APD.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6fb0cc17a040d803a597304620202423f646f294
When doing CSI stress test after cpu hotplug, sometimes, system
will hang in CSI test. After some debug, we find that if slow
down the APD NIC frequency before power on the offline CPU,
the issue is gone. For now, just add such SW workaround.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I39a49efc382fbebf46e1ff15c93d506bd5f6bec1
Enable the AFBB by default for active mode when APD side wakeup
from low power mode to align with the first time boot up.
Update the power mode configs to force shutdown all the
necessary power switches to optimize the power consumption.
To reduce the pad power consumption, put all the pad into
OFF mode to save more power. the PTD's compensation should
also be disabled in low power mode to save more power.
when APD enters PD mode, the LDO1(used by DDR) can be shutdown
to save power. when APD enters DPD mode, the BUCK3(supply for
APD/LPAV) can be shutdown to save power.
In single boot mode, When APD enters DPD mode, buck3 will
shutdown, LDO1 should be off to save more power as the DDR
controller has lost power.
In dualboot mode, the LPAV is owned by RTD side. When APD enters
low power mode, APD side should not config those PMIC regulators
that used by the resource owned by RTD side.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie5e9b428f85345b81744313a8fb93bfc27e0dd71
On i.MX8ULP, we need to use the APD deep power down(DPD) mode
to support the system power off function. when APD enter
power off mode, only the RTD can re-kick it and boot from ROM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifb42db0a7cf87b932160c59b47eca4d0f08f8cdf
The APD can be put into PD mode when linux suspend(mem). This patch
add the support for it. As the whole AP domain's context will be lost,
so we must save the necessary HW module states before entering PD mode,
and we need to restore those contexts when system wake up. Fot details
about which HW module's state will be lost, please refer to the RM.
When APD enter PD mode, only the wakeup event connected to the WUU
can wakeup APD successfully. The upower wakeup source is used to
wakeup APD by RTD due to the factor that the MU between A core & M
core is not connected into WUU to generate wakeup event.
as the SRAM0 will be power down when APD enters PD mode, so we
need to re-init the scmi channels(resides in the SRAM0). otherwise
the SCMI can NOT work anymore.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I44b0cdc8397e5d6a82081ea6746542e9fa4b9fc1
Add basic support for the cpuidle(cluster retention) and system
suspend support using the HW sleep mode.
When system enter low power mode after doing reboot twice, APD
will be failed to exit from low power mode successfully. it is
because that after secondary reboot, upower will modify the default
power switch config, then DDR will be off wrongly. So config the
low power mode info explicitly before APD entering any low power
mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ib68bfdfd4b925541e343aef4a5296a542451f86b
Add the basic support for i.MX8ULP.
The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an Arm Cortex-M33. This combined architecture enables the
device to run a rich operating system (such as Linux) on
the Cortex-A35 core and an RTOS (such as FreeRTOS) on the
Cortex-M33 core. It also includes a Cadence Tensilica Fusion
DSP for low-power audio and a HiFi4 DSP for advanced audio
and machine learning applications.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
