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https://github.com/ARM-software/arm-trusted-firmware.git
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fcd41e8692
Add the basic support for i.MX8ULP. The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm Cortex-A35 cores alongside an Arm Cortex-M33. This combined architecture enables the device to run a rich operating system (such as Linux) on the Cortex-A35 core and an RTOS (such as FreeRTOS) on the Cortex-M33 core. It also includes a Cadence Tensilica Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine learning applications. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/*
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* Copyright 2021-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv3.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat_imx8.h>
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static uintptr_t secure_entrypoint;
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#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
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#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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#define RVBARADDRx(c) (IMX_SIM1_BASE + 0x5c + 0x4 * (c))
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#define WKPUx(c) (IMX_SIM1_BASE + 0x3c + 0x4 * (c))
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#define AD_COREx_LPMODE(c) (IMX_CMC1_BASE + 0x50 + 0x4 * (c))
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static int imx_pwr_set_cpu_entry(unsigned int cpu, unsigned int entry)
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{
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mmio_write_32(RVBARADDRx(cpu), entry);
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/* set update bit */
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mmio_write_32(IMX_SIM1_BASE + 0x8, mmio_read_32(IMX_SIM1_BASE + 0x8) | BIT_32(24 + cpu));
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/* wait for ack */
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while (!(mmio_read_32(IMX_SIM1_BASE + 0x8) & BIT_32(26 + cpu))) {
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}
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/* clear update bit */
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mmio_write_32(IMX_SIM1_BASE + 0x8, mmio_read_32(IMX_SIM1_BASE + 0x8) & ~BIT_32(24 + cpu));
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/* clear ack bit */
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mmio_write_32(IMX_SIM1_BASE + 0x8, mmio_read_32(IMX_SIM1_BASE + 0x8) | BIT_32(26 + cpu));
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return 0;
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}
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int imx_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int cpu = MPIDR_AFFLVL0_VAL(mpidr);
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imx_pwr_set_cpu_entry(cpu, secure_entrypoint);
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mmio_write_32(IMX_CMC1_BASE + 0x18, 0x3f);
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mmio_write_32(IMX_CMC1_BASE + 0x50 + 0x4 * cpu, 0);
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/* enable wku wakeup for idle */
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mmio_write_32(IMX_SIM1_BASE + 0x3c + 0x4 * cpu, 0xffffffff);
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return PSCI_E_SUCCESS;
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}
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void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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imx_pwr_set_cpu_entry(0, IMX_ROM_ENTRY);
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plat_gic_pcpu_init();
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plat_gic_cpuif_enable();
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}
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int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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return PSCI_E_SUCCESS;
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}
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void imx_pwr_domain_off(const psci_power_state_t *target_state)
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{
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unsigned int cpu = MPIDR_AFFLVL0_VAL(read_mpidr_el1());
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plat_gic_cpuif_disable();
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/* disable wakeup */
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mmio_write_32(WKPUx(cpu), 0);
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mmio_write_32(AD_COREx_LPMODE(cpu), 0x3);
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}
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void __dead2 imx8ulp_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
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{
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while (1) {
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wfi();
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}
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}
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void __dead2 imx8ulp_system_reset(void)
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{
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imx_pwr_set_cpu_entry(0, IMX_ROM_ENTRY);
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/* Write invalid command to WDOG CNT to trigger reset */
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mmio_write_32(IMX_WDOG3_BASE + 0x4, 0x12345678);
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while (true) {
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wfi();
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}
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}
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static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_on = imx_pwr_domain_on,
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.pwr_domain_on_finish = imx_pwr_domain_on_finish,
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.validate_ns_entrypoint = imx_validate_ns_entrypoint,
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.system_reset = imx8ulp_system_reset,
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.pwr_domain_off = imx_pwr_domain_off,
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.pwr_domain_pwr_down_wfi = imx8ulp_pwr_domain_pwr_down_wfi,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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secure_entrypoint = sec_entrypoint;
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imx_pwr_set_cpu_entry(0, sec_entrypoint);
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*psci_ops = &imx_plat_psci_ops;
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mmio_write_32(IMX_CMC1_BASE + 0x18, 0x3f);
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mmio_write_32(IMX_SIM1_BASE + 0x3c, 0xffffffff);
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return 0;
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}
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