Cortex-A715 erratum 2804830 applies to r0p0, r1p0, r1p1 and r1p2,
and is fixed in r1p3.
Under some conditions, writes of a 64B-aligned, 64B granule of
memory might cause data corruption without this workaround. See SDEN
for details.
Since this workaround disables write streaming, it is expected to
have a significant performance impact for code that is heavily
reliant on write streaming, such as memcpy or memset.
SDEN: https://developer.arm.com/documentation/SDEN-2148827/latest/
Change-Id: Ia12f6c7de7c92f6ea4aec3057b228b828d48724c
Signed-off-by: John Powell <john.powell@arm.com>
`r3` is used to pass the base address of the transfer list. Make sure we
update the context structure with this register value so it is populated
with this information prior to executing the next stage.
Change-Id: Ie1eedbd2eb68b592df30779625691e8975d987bf
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add firmware handoff to BL32 sources to provide support for the
framework in SP-MIN.
Change-Id: Ida8713fef8ba8fa72146004e41bf40f1a6b6f5ca
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Introduce the 32-bit variant of the SRAM layout used by BL1 to
communicate available free SRAM to BL2. This layout was added to the
specification in:
https://github.com/FirmwareHandoff/firmware_handoff/pull/54.
Change-Id: I559fb8a00725eaedf01856af42d73029802aa095
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add the 32-bit version of the entry_point_info structure used to pass
the boot arguments for future executables, added to the spec under the
PR: https://github.com/FirmwareHandoff/firmware_handoff/pull/54.
Change-Id: Id98e0f98db6ffd4790193e201f24e62101450e20
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
The current implementation uses the `r12` register as temporary storage
for r4. However, `r12` is a call-clobbered register, meaning its
contents are not preserved across function calls. This becomes
problematic when we later call the `zeromem` function, as any
information stored in `r12` will be lost. To address this issue, we
should avoid using `r12` to store boot parameters.
Change-Id: If94b7fc3a01bc617ceadaaa704d5aa5e5accfd3f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Initializing the transfer list using `transfer_list_ensure` allows reuse
of an already initialized transfer list. While this is beneficial when
receiving a transfer list and ensuring one exists, it causes issues
during a system RESET if the old content of SRAM is not cleared.
To prevent this, at least one step in the reset path must zero intialise
the transfer list memory. Unless a previous stage explicitly provides a
transfer list via boot arguments, a fresh transfer list should be
created.
This change ensures that BL1 and BL31 properly reinitialize the transfer
lists, preserving correctness for secure and non-secure handoffs in
TF-A.
Change-Id: I3bfaa9e76df932a637031d645e4a22d857a094a5
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Some APIs, like `transfer_list_check_header`, are used preemptively to
determine if a new TL needs to be initialized. If we validate a TL and
anticipate its contents to be invalid or corrupted, logging these as
error message isn't helpful.
Change-Id: Ic22378828548d48f73aa74d494f110fbd11857f4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Support all the FCS(FPGA Crypto Service) commands with
SiPSVC verson3 framework.
Change-Id: I1dfb95aaddf7111325ce0082eb26f7a201001141
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>
- Develop SiPSVC-V3 framework to support async/yielding SMC calls.
- Add support for multi clients with multiple jobs running together.
- Add support for SDM doorbell interrupt handling.
- Keep the framework backward compatible with V1 clients.
- Enable the framework on all the platform Agilex7, Agilex5, N5X,
and Stratix10.
Change-Id: I9eb61c48be89867b4227e084493bfcf67cbe7924
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>
This patch also checks for FEAT_HCX before enabling FEAT_MOPS
when INIT_UNUSED_NS_EL1 = 1 and adds build dependency check.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iff4a068aa392fc8d29e2e4da7a2e7df0b3104e65
When building with Buildroot environment, the rule to build
the object is not used from the Makefile but from another one with
a higher priority.
It leads to the following error:
Built fiptool successfully
EL3 Runtime Firmware BL31: offset=0x88, size=0xE401, cmdline="--soc-fw"
Non-Trusted Firmware BL33: offset=0xE489, size=0xD1438, cmdline="--nt-fw"
Wall -Werror -pedantic -std=c99 -O2 -DVERSION='"v2.12.0(release):master"' -D_GNU_SOURCE -D_XOPEN_SOURCE=700 -c -o create_pbl.o create_pbl.c
make[3]: Wall: No such file or directory
Let's be explicit in order to enforce the local rule. There is not .h
file so it should be removed from the dependency list in oder to avoid
such error:
make[3]: *** No rule to make target 'create_pbl.h', needed by 'create_pbl.o'. Stop.
Change-Id: Idec378c5688e332695d805f3fca2800d905a1c74
Signed-off-by: Vincent Jardin <vjardin@free.fr>
This patch only arranged the case numbers that were incorrectly
ordered.
Change-Id: I0da48c68c5c2f4b5ba19ab770377ea91066bcb6a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This patch provides architectural support for further use of
Memory Encryption Contexts (MEC) by declaring the necessary
registers, bits, masks, helpers and values and modifying the
necessary registers to enable FEAT_MEC.
Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I670dbfcef46e131dcbf3a0b927467ebf6f438fa4
Husky 9.1 now warns when doing some rebase of patches:
husky - DEPRECATED
Please remove the following two lines from .husky/prepare-commit-msg:
#!/usr/bin/env sh
. "$(dirname -- "$0")/_/husky.sh"
They WILL FAIL in v10.0.0
Remove the deprecated lines.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8b7fa82aa7b5e178554a1b4a650b2b1b8044092c
* changes:
build(dev-deps): bump the dev-deps group across 1 directory with 5 updates
build(dev-deps): bump the dev-deps group across 3 directories with 9 updates
More recent versions of Poetry introduced the `package-mode` key to
configure whether the project should be used for dependency management
only, but this is incompatible with the earlier versions of Poetry that
we still support.
Instead, we rely on installing with the `--no-root` flag, which behaves
similarly. Installing without passing the `--no-root` flag is
deprecated, and in recent versions of Poetry has become a hard error.
This change ensures that the build system always installs dependencies
with the required flag.
Change-Id: Ic1543511314dcd20c00b73fd9e8cfae3dd034a41
Signed-off-by: Chris Kay <chris.kay@arm.com>
This corrects the MISRA violation C2012-17.8:
A function parameter should not be modified.
Local variable is declared and used to process the value
from the argument.
Change-Id: Ia757db4903132794623dbf92ff8cecc9b40f170d
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-17.8:
A function parameter should not be modified.
Local variable is declared and used to process the value
from the argument.
Change-Id: I94e8048c43f767ad08820624b7c7e43b0a3e9190
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-17.7:
The value returned by a function having non-void return type shall
be used.
Typecast the function call to void to discard the return value.
Change-Id: I7cfb11bb34bc44a4985d30d37d8cce4b8d241652
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-5.8:
Identifiers that define objects or functions with
external linkage shall be unique.
Modify the variable name to prevent conflict with
external function declaration
Change-Id: I2f109242b6dd3b3c5e9289881e3dd5466c74fcb5
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.
Change-Id: Ibadebf8fd5206eb079535d2775d1877b42f1eab7
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer in the function arguments.
Change-Id: Id3d4aa528f275973a37c0b9af04495632cb2dda3
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer in the function arguments.
Change-Id: Idf4b8ea7842304849242a06d6ada73f11afc8cde
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer in the function arguments.
Change-Id: Ia323a2b2946d61a639696e2559f88e376beda861
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I4276035b3e7a223e80712e023457662689a011a1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I1500e2b3628313e68f94bce701a057b80bc2f933
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.7:
If a composite expression is used as one operand of an operator in
which the usual arithmetic conversions are performed then the other
operand shall not have wider essential type.
Explicitly type casted to match the data type of both the operands.
Change-Id: I89fef817ad672f310de9bc0e93646cd2ba04793b
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This corrects the MISRA violation C2012-10.6:
The value of a composite expression shall not be assigned to
an object with wider essential type.
Explicitly type casted to match the data type of composite
expression.
Change-Id: I2ec044ff7fd7a8d0cdc8db5f71f30872fb8d9e81
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Perform sanity checks on the launch features received via DRTM parameters.
Return INVALID_PARAMETERS if they are incorrect.
Change-Id: I7e8068154028d1c8f6b6b45449616bb5711ea76e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Introduce a new EXTRACT_FIELD macro to simplify the extraction
of specific fields from a value by shifting the value right
and applying the mask.
Change-Id: Iae9573d6d23067bbde13253e264e4f6f18b806c2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
tspd compiles with `arch_helpers.h` and when FEAT_D128 is enabled
read/writes to D128 impacted registers will provide 128-bit
mrrs/msrr read/write implementation.
However FEAT_D128 implementation with SCR_EL3.D128en is set only
for lower-EL Non-Secure world. When tspd is chosen as the SPD target,
it builds tsp as well. This S-EL1 payload, used for testing,
inadvertently uses mrrs/msrr read/write implementation in
`modify_el1_common_regs` helper function. This eventually leads
to a panic.
Group all D128 impacted registers and avoid using mrrs/msrr read/write
implementation for tspd builds.
Change-Id: Ic0ed3a901ffa65f9447cae08951defbadee3e02a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
