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fix(cpufeat): avoid using mrrs/msrr for tspd

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tspd compiles with `arch_helpers.h` and when FEAT_D128 is enabled
read/writes to D128 impacted registers will provide 128-bit
mrrs/msrr read/write implementation.

However FEAT_D128 implementation with SCR_EL3.D128en is set only
for lower-EL Non-Secure world. When tspd is chosen as the SPD target,
it builds tsp as well. This S-EL1 payload, used for testing,
inadvertently uses mrrs/msrr read/write implementation in
`modify_el1_common_regs` helper function. This eventually leads
to a panic.

Group all D128 impacted registers and avoid using mrrs/msrr read/write
implementation for tspd builds.

Change-Id: Ic0ed3a901ffa65f9447cae08951defbadee3e02a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2025-03-07 09:30:42 -06:00
parent f2d12fce88
commit f3e2b49970
1 changed files with 32 additions and 25 deletions
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57
include/arch/aarch64/arch_helpers.h
View file

@ -264,11 +264,41 @@ void disable_mpu_icache_el2(void);
#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
#if ENABLE_FEAT_D128
#if ENABLE_FEAT_D128 && !defined(SPD_tspd)
/* Don't use mrrs/msrr read/write implementation with tspd,
* While using SPD=tspd, tspd compiles with current arch_helpers
* thus trying to use mrrs/msrr read/write from Secure-world.
* SCR_EL3.D128en is set only for Non-Secure world, which may cause
* panic while using mrrs/msrr from tspd secure world.
*/
DECLARE_SYSREG128_RW_FUNCS(par_el1)
DECLARE_SYSREG128_RW_FUNCS(ttbr0_el1)
DECLARE_SYSREG128_RW_FUNCS(ttbr1_el1)
DECLARE_SYSREG128_RW_FUNCS(ttbr0_el2)
DECLARE_SYSREG128_RW_FUNCS(ttbr1_el2)
DECLARE_SYSREG128_RW_FUNCS(vttbr_el2)
/* FEAT_THE Registers */
DECLARE_SYSREG128_RW_FUNCS(rcwmask_el1)
DECLARE_SYSREG128_RW_FUNCS(rcwsmask_el1)
#else
DEFINE_SYSREG_RW_FUNCS(par_el1)
#endif
DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
/* FEAT_THE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1)
#endif /* ENABLE_FEAT_D128 && !defined(SPD_tspd) */
DEFINE_IDREG_READ_FUNC(id_pfr1_el1)
DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1)
@ -450,20 +480,6 @@ DEFINE_SYSREG_RW_FUNCS(tcr_el1)
DEFINE_SYSREG_RW_FUNCS(tcr_el2)
DEFINE_SYSREG_RW_FUNCS(tcr_el3)
#if ENABLE_FEAT_D128
DECLARE_SYSREG128_RW_FUNCS(ttbr0_el1)
DECLARE_SYSREG128_RW_FUNCS(ttbr1_el1)
DECLARE_SYSREG128_RW_FUNCS(ttbr0_el2)
DECLARE_SYSREG128_RW_FUNCS(ttbr1_el2)
DECLARE_SYSREG128_RW_FUNCS(vttbr_el2)
#else
DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
#endif
DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
DEFINE_SYSREG_RW_FUNCS(cptr_el2)
@ -706,15 +722,6 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
/* FEAT_THE Registers */
#if ENABLE_FEAT_D128
DECLARE_SYSREG128_RW_FUNCS(rcwmask_el1)
DECLARE_SYSREG128_RW_FUNCS(rcwsmask_el1)
#else
DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1)
#endif
/* FEAT_SCTLR2 Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)