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fix(intel): this patch is used to solve DDR and VAB

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The patch provide solutions for:
1. Enable BL31 console logs during run-time.
2. Update VAB initialization.
3. Update DDR size accordin to Linux DTS configuration.
4. Solve VAB CCERT address issue.

Change-Id: I41eb0fab747de5010d369e845c33a45decb41e21
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
This commit is contained in:
Jit Loon Lim 2025-03-05 10:44:47 +08:00
parent e5a1f4abee
commit 458b40df58
4 changed files with 17 additions and 12 deletions
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5
plat/intel/soc/agilex/bl2_plat_setup.c
View file

@ -1,7 +1,7 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -190,7 +190,8 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
ret = socfpga_vab_init(image_id);
if (ret < 0) {
ERROR("SOCFPGA VAB Authentication failed\n");
wfi();
while (1)
wfi();
}
#endif

6
plat/intel/soc/agilex5/bl31_plat_setup.c
View file

@ -61,6 +61,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
/* Enable TF-A BL31 logs when running from non-secure world also. */
console_set_scope(&console,
(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
setup_smmu_stream_id();
/*
@ -290,7 +294,7 @@ void bl31_plat_set_secondary_cpu_off(void)
void bl31_plat_runtime_setup(void)
{
console_switch_state(CONSOLE_FLAG_RUNTIME|CONSOLE_FLAG_BOOT);
/* Dummy override function. */
}
void bl31_plat_enable_mmu(uint32_t flags)

10
plat/intel/soc/agilex5/soc/agilex5_ddr.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -370,10 +370,10 @@ int agilex5_ddr_init(handoff *hoff_ptr)
/* DDR size queried from the IOSSM controller */
hw_ddr_size = (phys_size_t)io96b_ctrl.overall_size * SZ_1G / SZ_8;
/* TODO: Hard code 1GB as of now, and DDR start and end address */
config_ddr_size = 0x40000000;
ddr_info_set[0].start = 0x80000000;
ddr_info_set[0].size = 0x40000000;
/* TODO: To update config_ddr_size by using FDT in the future. */
config_ddr_size = 0x80000000;
ddr_info_set[0].start = DRAM_BASE;
ddr_info_set[0].size = hw_ddr_size;
if (config_ddr_size != hw_ddr_size) {
WARN("DDR: DDR size configured is (%lld MiB)\n", config_ddr_size >> 20);

8
plat/intel/soc/common/socfpga_vab.c
View file

@ -1,7 +1,7 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -113,10 +113,10 @@ int socfpga_vab_authentication(void **p_image, size_t *p_size)
VERBOSE("mbox_data_addr = %lx mbox_data_sz = %d\n", mbox_data_addr, mbox_data_sz);
memcpy_s(mbox_relocate_data_addr, mbox_data_sz * sizeof(uint32_t),
(uint8_t *)mbox_data_addr, mbox_data_sz * sizeof(uint32_t));
memcpy_s(mbox_relocate_data_addr, (mbox_data_sz * sizeof(uint32_t)) / MBOX_WORD_BYTE,
(uint8_t *)mbox_data_addr, (mbox_data_sz * sizeof(uint32_t)) / MBOX_WORD_BYTE);
*((unsigned int *)mbox_relocate_data_addr) = CCERT_CMD_TEST_PGM_MASK;
*((unsigned int *)mbox_relocate_data_addr) = 0;
do {
/* Invoke SMC call to ATF to send the VAB certificate to SDM */