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fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT

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This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
internal macro FFH_SUPPORT which gets enabled when platforms wants
to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT
will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled.
FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files
to provide equivalent check which was provided by RAS_FFH_SUPPORT
earlier. In generic code we needed a macro which could abstract both
HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations.
Former was tied up with NS world only while the latter was tied to RAS
feature.

This is to allow Secure/Realm world to have their own FFH macros
in future.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73
This commit is contained in:
Manish Pandey 2023-10-10 15:42:19 +01:00
parent 970a4a8d8c
commit f87e54f73c
29 changed files with 78 additions and 75 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
Makefile
View file

@ -809,6 +809,14 @@ else
BL2_RUNS_AT_EL3 := 0
endif
# This internal flag is set to 1 when Firmware First handling of External aborts
# is required by lowe ELs. Currently only NS requires this support.
ifeq ($(HANDLE_EA_EL3_FIRST_NS),1)
FFH_SUPPORT := 1
else
FFH_SUPPORT := 0
endif
$(eval $(call MAKE_PREREQ_DIR,${BUILD_PLAT}))
ifeq (${ARM_ARCH_MAJOR},7)
@ -970,18 +978,9 @@ endif
# RAS_EXTENSION is deprecated, provide alternate build options
ifeq ($(RAS_EXTENSION),1)
$(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS \
and RAS_FFH_SUPPORT instead")
and HANDLE_EA_EL3_FIRST_NS instead")
endif
# RAS firmware first handling requires that EAs are handled in EL3 first
ifeq ($(RAS_FFH_SUPPORT),1)
ifneq ($(ENABLE_FEAT_RAS),1)
$(error For RAS_FFH_SUPPORT, ENABLE_FEAT_RAS must also be 1)
endif
ifneq ($(HANDLE_EA_EL3_FIRST_NS),1)
$(error For RAS_FFH_SUPPORT, HANDLE_EA_EL3_FIRST_NS must also be 1)
endif
endif #(RAS_FFH_SUPPORT)
# When FAULT_INJECTION_SUPPORT is used, require that FEAT_RAS is enabled
ifeq ($(FAULT_INJECTION_SUPPORT),1)
@ -1284,6 +1283,7 @@ $(eval $(call assert_booleans,\
ENABLE_SME_FOR_SWD \
ENABLE_SVE_FOR_SWD \
ENABLE_FEAT_RAS \
FFH_SUPPORT \
ERROR_DEPRECATED \
FAULT_INJECTION_SUPPORT \
GENERATE_COT \
@ -1338,7 +1338,6 @@ $(eval $(call assert_booleans,\
ERRATA_ABI_SUPPORT \
ERRATA_NON_ARM_INTERCONNECT \
CONDITIONAL_CMO \
RAS_FFH_SUPPORT \
PSA_CRYPTO \
ENABLE_CONSOLE_GETC \
)))
@ -1444,6 +1443,7 @@ $(eval $(call add_defines,\
ENABLE_SVE_FOR_NS \
ENABLE_SVE_FOR_SWD \
ENABLE_FEAT_RAS \
FFH_SUPPORT \
ENCRYPT_BL31 \
ENCRYPT_BL32 \
ERROR_DEPRECATED \
@ -1461,7 +1461,6 @@ $(eval $(call add_defines,\
PROGRAMMABLE_RESET_ADDRESS \
PSCI_EXTENDED_STATE_ID \
PSCI_OS_INIT_MODE \
RAS_FFH_SUPPORT \
RESET_TO_BL31 \
SEPARATE_CODE_AND_RODATA \
SEPARATE_BL2_NOLOAD_REGION \

4
bl31/aarch64/ea_delegate.S
View file

@ -292,7 +292,7 @@ endfunc reflect_pending_async_ea_to_lower_el
* x1: EA syndrome
*/
func delegate_sync_ea
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS
/*
* Check for Uncontainable error type. If so, route to the platform
* fatal error handler rather than the generic EA one.
@ -322,7 +322,7 @@ endfunc delegate_sync_ea
* x1: EA syndrome
*/
func delegate_async_ea
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS
/* Check Exception Class to ensure SError, as this function should
* only be invoked for SError. If that is not the case, which implies
* either an HW error or programming error, panic.

4
bl31/aarch64/runtime_exceptions.S
View file

@ -60,7 +60,7 @@
synchronize_errors
mrs x30, ISR_EL1
tbz x30, #ISR_A_SHIFT, 2f
#if HANDLE_EA_EL3_FIRST_NS
#if FFH_SUPPORT
mrs x30, scr_el3
tst x30, #SCR_EA_BIT
b.eq 1f
@ -175,7 +175,7 @@ vector_entry fiq_sp_elx
end_vector_entry fiq_sp_elx
vector_entry serror_sp_elx
#if HANDLE_EA_EL3_FIRST_NS
#if FFH_SUPPORT
/*
* This will trigger if the exception was taken due to SError in EL3 or
* because of pending asynchronous external aborts from lower EL that got

16
docs/components/ras.rst
View file

@ -63,17 +63,19 @@ will be added in future**
TF-A build options
==================
- **ENABLE_FEAT_RAS**: Manage FEAT_RAS extension when switching the world.
- **RAS_FFH_SUPPORT**: Pull in necessary framework and platform hooks for Firmware first
handling(FFH) of RAS errors.
- **ENABLE_FEAT_RAS**: Enable RAS extension feature at EL3.
- **HANDLE_EA_EL3_FIRST_NS**: Required for FFH
- **RAS_TRAP_NS_ERR_REC_ACCESS**: Trap Non-secure access of RAS error record registers.
- **RAS_EXTENSION**: Deprecated macro, equivalent to ENABLE_FEAT_RAS and RAS_FFH_SUPPORT
put together.
- **RAS_EXTENSION**: Deprecated macro, equivalent to ENABLE_FEAT_RAS and
HANDLE_EA_EL3_FIRST_NS put together.
RAS internal macros
- **FFH_SUPPORT**: Gets enabled if **HANDLE_EA_EL3_FIRST_NS** is enabled.
RAS feature has dependency on some other TF-A build flags
- **EL3_EXCEPTION_HANDLING**: Required for FFH
- **HANDLE_EA_EL3_FIRST_NS**: Required for FFH
- **FAULT_INJECTION_SUPPORT**: Required for testing RAS feature on fvp platform
RAS Framework
@ -238,7 +240,7 @@ Engaging the RAS framework
Enabling RAS support is a platform choice
The RAS support in |TF-A| introduces a default implementation of
``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_FFH_SUPPORT``
``plat_ea_handler``, the External Abort handler in EL3. When ``ENABLE_FEAT_RAS``
is set to ``1``, it'll first call ``ras_ea_handler()`` function, which is the
top-level RAS exception handler. ``ras_ea_handler`` is responsible for iterating
to through platform-supplied error records, probe them, and when an error is

7
docs/getting_started/build-internals.rst
View file

@ -12,3 +12,10 @@ depends on certain options to be enabled or disabled.
interest when Armv8.4-SecEL2 or RME extension is implemented.
Default is 0 (disabled). This option will be set to 1 (enabled) when ``SPD=spmd``
and ``SPMD_SPM_AT_SEL2`` is set or when ``ENABLE_RME`` is set to 1 (enabled).
- ``FFH_SUPPORT``: This boolean option provides support to enable Firmware First
handling (FFH) of External aborts and SError interrupts originating from lower
ELs which gets trapped in EL3. This option will be set to 1 (enabled) if
``HANDLE_EA_EL3_FIRST_NS`` is set. Currently only NS world routes EA to EL3 but
in future when Secure/Realm wants to use FFH then they can introduce new macros
which will enable this option implicitly.

6
docs/getting_started/build-options.rst
View file

@ -811,17 +811,13 @@ Common build options
- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI
OS-initiated mode. This option defaults to 0.
- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features
- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features
are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
or later CPUs. This flag can take the values 0 or 1. The default value is 0.
NOTE: This flag enables use of IESB capability to reduce entry latency into
EL3 even when RAS error handling is not performed on the platform. Hence this
flag is recommended to be turned on Armv8.2 and later CPUs.
- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors
originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``,
``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``.
- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
entrypoint) or 1 (CPU reset to BL31 entrypoint).

17
docs/porting-guide.rst
View file

@ -3298,10 +3298,10 @@ Function : plat_ea_handler
Argument : uint64_t
Return : void
This function is invoked by the RAS framework for the platform to handle an
External Abort received at EL3. The intention of the function is to attempt to
resolve the cause of External Abort and return; if that's not possible, to
initiate orderly shutdown of the system.
This function is invoked by the runtime exception handling framework for the
platform to handle an External Abort received at EL3. The intention of the
function is to attempt to resolve the cause of External Abort and return;
if that's not possible then an orderly shutdown of the system is initiated.
The first parameter (``int ea_reason``) indicates the reason for External Abort.
Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
@ -3316,13 +3316,8 @@ The third parameter (``void *cookie``) is unused for now. The fourth parameter
(``uint64_t flags``) indicates the preempted security state. These parameters
are received from the top-level exception handler.
If ``RAS_FFH_SUPPORT`` is set to ``1``, the default implementation of this
function iterates through RAS handlers registered by the platform. If any of the
RAS handlers resolve the External Abort, no further action is taken.
If ``RAS_FFH_SUPPORT`` is set to ``0``, or if none of the platform RAS handlers
could resolve the External Abort, the default implementation prints an error
message, and panics.
This function must be implemented if a platform expects Firmware First handling
of External Aborts.
Function : plat_handle_uncontainable_ea
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

2
include/lib/el3_runtime/aarch64/context.h
View file

@ -71,7 +71,7 @@
* KFH mode : Used as counter value
*/
#define CTX_NESTED_EA_FLAG U(0x48)
#if HANDLE_EA_EL3_FIRST_NS
#if FFH_SUPPORT
#define CTX_SAVED_ESR_EL3 U(0x50)
#define CTX_SAVED_SPSR_EL3 U(0x58)
#define CTX_SAVED_GPREG_LR U(0x60)

2
include/plat/arm/common/arm_def.h
View file

@ -774,7 +774,7 @@ MEASURED_BOOT
#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
/* Priority levels for ARM platforms */
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
#define PLAT_RAS_PRI 0x10
#endif
#define PLAT_SDEI_CRITICAL_PRI 0x60

3
make_helpers/defaults.mk
View file

@ -191,9 +191,6 @@ PSCI_EXTENDED_STATE_ID := 0
# Enable PSCI OS-initiated mode support
PSCI_OS_INIT_MODE := 0
# Enable RAS Firmware First Handling Support
RAS_FFH_SUPPORT := 0
# By default, BL1 acts as the reset handler, not BL31
RESET_TO_BL31 := 0

19
plat/arm/board/fvp/platform.mk
View file

@ -397,8 +397,12 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
endif
endif
ifeq (${RAS_FFH_SUPPORT},1)
ifeq (${HANDLE_EA_EL3_FIRST_NS},1)
ifeq (${ENABLE_FEAT_RAS},1)
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
else
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
endif
endif
ifneq (${ENABLE_STACK_PROTECTOR},0)
@ -518,16 +522,19 @@ endif
# Test specific macros, keep them at bottom of this file
$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
ifeq (${PLATFORM_TEST_EA_FFH}, 1)
ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
$(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1")
ifeq (${FFH_SUPPORT}, 0)
$(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1")
endif
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
endif
$(eval $(call add_define,PLATFORM_TEST_RAS_FFH))
ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
ifeq (${RAS_EXTENSION}, 0)
$(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1")
ifeq (${ENABLE_FEAT_RAS}, 0)
$(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1")
endif
ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
$(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1")
endif
endif

2
plat/arm/board/rdn2/platform.mk
View file

@ -69,7 +69,7 @@ BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
endif
ifeq (${RAS_FFH_SUPPORT},1)
ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1)
BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \
${CSS_ENT_BASE}/ras/sgi_ras_common.c \
${CSS_ENT_BASE}/ras/sgi_ras_sram.c \

2
plat/arm/board/rdn2/rdn2_plat.c
View file

@ -137,7 +137,7 @@ void bl31_platform_setup(void)
sgi_bl31_common_platform_setup();
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
sgi_ras_platform_setup(&ras_config);
#endif
}

2
plat/arm/board/rdn2/rdn2_security.c
View file

@ -15,7 +15,7 @@
static const arm_tzc_regions_info_t tzc_regions[] = {
ARM_TZC_REGIONS_DEF,
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
RDN2_TZC_CPER_REGION,
#endif
{}

2
plat/arm/board/tc/platform.mk
View file

@ -21,8 +21,6 @@ CSS_USE_SCMI_SDS_DRIVER := 1
ENABLE_FEAT_RAS := 1
RAS_FFH_SUPPORT := 0
SDEI_SUPPORT := 0
EL3_EXCEPTION_HANDLING := 0

2
plat/arm/common/arm_bl31_setup.c
View file

@ -295,7 +295,7 @@ void arm_bl31_platform_setup(void)
/* Initialize power controller before setting up topology */
plat_arm_pwrc_setup();
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
ras_init();
#endif

2
plat/arm/common/arm_common.mk
View file

@ -352,7 +352,7 @@ endif
endif
# RAS sources
ifeq (${RAS_FFH_SUPPORT},1)
ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1)
BL31_SOURCES += lib/extensions/ras/std_err_record.c \
lib/extensions/ras/ras_common.c
endif

2
plat/arm/common/arm_gicv3.c
View file

@ -41,7 +41,7 @@ static const uintptr_t *gicr_frames = gicr_base_addrs;
static const interrupt_prop_t arm_interrupt_props[] = {
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0),
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0,
GIC_INTR_CFG_LEVEL)
#endif

6
plat/arm/css/sgi/include/sgi_base_platform_def.h
View file

@ -204,13 +204,13 @@
SOC_CSS_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
#define PLAT_SP_PRI PLAT_RAS_PRI
#else
#define PLAT_SP_PRI 0x10
#endif
#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && RAS_FFH_SUPPORT
#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && ENABLE_FEAT_RAS && FFH_SUPPORT
/*
* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
* memory shared between EL3 and S-EL0.
@ -239,7 +239,7 @@
*/
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
#endif /* SPM_MM && RAS_FFH_SUPPORT */
#endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)

2
plat/arm/css/sgi/sgi-common.mk
View file

@ -10,8 +10,6 @@ CSS_ENT_BASE := plat/arm/css/sgi
ENABLE_FEAT_RAS := 1
RAS_FFH_SUPPORT := 0
SDEI_SUPPORT := 0
EL3_EXCEPTION_HANDLING := 0

2
plat/arm/css/sgi/sgi_plat.c
View file

@ -93,7 +93,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_ARM_SECURE_MAP_DEVICE,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
CSS_SGI_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,

2
plat/arm/css/sgi/sgi_plat_v2.c
View file

@ -87,7 +87,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = {
SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
CSS_SGI_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,

8
plat/common/aarch64/plat_common.c
View file

@ -11,7 +11,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/console.h>
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS
#include <lib/extensions/ras.h>
#endif
#include <lib/xlat_tables/xlat_mmu_helpers.h>
@ -29,7 +29,9 @@
#pragma weak plat_sdei_validate_entry_point
#endif
#if FFH_SUPPORT
#pragma weak plat_ea_handler = plat_default_ea_handler
#endif
void bl31_plat_runtime_setup(void)
{
@ -77,11 +79,12 @@ const char *get_el_str(unsigned int el)
return "EL1";
}
#if FFH_SUPPORT
/* Handler for External Aborts from lower EL including RAS errors */
void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags)
{
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS
/* Call RAS EA handler */
int handled = ras_ea_handler(ea_reason, syndrome, cookie, handle, flags);
if (handled != 0)
@ -99,3 +102,4 @@ void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *co
*/
lower_el_panic();
}
#endif

4
plat/common/aarch64/plat_ehf.c
View file

@ -12,7 +12,7 @@
* Enumeration of priority levels on ARM platforms.
*/
ehf_pri_desc_t plat_exceptions[] = {
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
/* RAS Priority */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_RAS_PRI),
#endif
@ -26,7 +26,7 @@ ehf_pri_desc_t plat_exceptions[] = {
#endif
#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
#if (PLAT_SP_PRI != PLAT_RAS_PRI)
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
#endif

2
plat/nvidia/tegra/include/tegra_private.h
View file

@ -154,7 +154,7 @@ int plat_sip_handler(uint32_t smc_fid,
void *handle,
uint64_t flags);
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS && FFH_SUPPORT
void tegra194_ras_enable(void);
void tegra194_ras_corrected_err_clear(uint64_t *cookie);
#endif

2
plat/nvidia/tegra/soc/t194/plat_ras.c
View file

@ -484,7 +484,7 @@ REGISTER_RAS_INTERRUPTS(carmel_ras_interrupts);
void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags)
{
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS
tegra194_ea_handler(ea_reason, syndrome, cookie, handle, flags);
#else
plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags);

2
plat/nvidia/tegra/soc/t194/plat_setup.c
View file

@ -254,7 +254,7 @@ void plat_early_platform_setup(void)
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS
/* Enable Uncorrectable RAS error */
tegra194_ras_enable();
#endif

2
plat/nvidia/tegra/soc/t194/plat_sip_calls.c
View file

@ -71,7 +71,7 @@ int32_t plat_sip_handler(uint32_t smc_fid,
break;
#if RAS_FFH_SUPPORT
#if ENABLE_FEAT_RAS
case TEGRA_SIP_CLEAR_RAS_CORRECTED_ERRORS:
{
/*

4
plat/nvidia/tegra/soc/t194/platform_t194.mk
View file

@ -37,7 +37,7 @@ $(eval $(call add_define,MAX_MMAP_REGIONS))
# enable RAS handling
HANDLE_EA_EL3_FIRST_NS := 1
RAS_FFH_SUPPORT := 1
ENABLE_FEAT_RAS := 1
# platform files
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
@ -71,7 +71,7 @@ BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S
endif
# RAS sources
ifeq (${RAS_FFH_SUPPORT},1)
ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1)
BL31_SOURCES += lib/extensions/ras/std_err_record.c \
lib/extensions/ras/ras_common.c \
${SOC_DIR}/plat_ras.c