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This patch removes RAS_FFH_SUPPORT macro which is the combination of ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an internal macro FFH_SUPPORT which gets enabled when platforms wants to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled. FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files to provide equivalent check which was provided by RAS_FFH_SUPPORT earlier. In generic code we needed a macro which could abstract both HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations. Former was tied up with NS world only while the latter was tied to RAS feature. This is to allow Secure/Realm world to have their own FFH macros in future. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73
97 lines
3.1 KiB
Makefile
97 lines
3.1 KiB
Makefile
# Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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RD_N2_VARIANTS := 0 1 2 3
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ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
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$(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
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$(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1, 2 or 3, currently \
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set to ${CSS_SGI_PLATFORM_VARIANT}.")
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endif
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$(eval $(call CREATE_SEQ,SEQ,4))
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ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
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$(error "Chip count for RD-N2-MC should be either $(SEQ) \
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currently it is set to ${CSS_SGI_CHIP_COUNT}.")
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endif
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# RD-N2 platform uses GIC-700 which is based on GICv4.1
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GIC_ENABLE_V4_EXTN := 1
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GIC_EXT_INTID := 1
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#Enable GIC Multichip Extension only for Multichip Platforms
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ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
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GICV3_IMPL_GIC600_MULTICHIP := 1
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endif
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override CSS_SYSTEM_GRACEFUL_RESET := 1
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override EL3_EXCEPTION_HANDLING := 1
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include plat/arm/css/sgi/sgi-common.mk
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RDN2_BASE = plat/arm/board/rdn2
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PLAT_INCLUDES += -I${RDN2_BASE}/include/
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SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
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lib/cpus/aarch64/neoverse_v2.S
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PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c
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BL1_SOURCES += ${SGI_CPU_SOURCES} \
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${RDN2_BASE}/rdn2_err.c
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BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \
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${RDN2_BASE}/rdn2_security.c \
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${RDN2_BASE}/rdn2_err.c \
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lib/utils/mem_region.c \
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drivers/arm/tzc/tzc400.c \
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plat/arm/common/arm_tzc400.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${RDN2_BASE}/rdn2_plat.c \
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${RDN2_BASE}/rdn2_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
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BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
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endif
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ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
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BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
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# Enable dynamic addition of MMAP regions in BL31
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BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
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endif
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ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1)
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BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \
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${CSS_ENT_BASE}/ras/sgi_ras_common.c \
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${CSS_ENT_BASE}/ras/sgi_ras_sram.c \
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${CSS_ENT_BASE}/ras/sgi_ras_cpu.c
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endif
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \
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${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
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FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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# Add the FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts
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NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
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# Add the NT_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
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override CTX_INCLUDE_AARCH32_REGS := 0
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override ENABLE_FEAT_AMU := 1
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