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Prevent speculative execution past ERET

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Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).

This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
679db70801
29fb48ace4
3a08873ece
abfd092aa1

It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c

Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
This commit is contained in:
Anthony Steinhauser 2020-01-07 15:44:06 -08:00
parent d81e38f66e
commit f461fe346b
11 changed files with 28 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
bl1/aarch64/bl1_exceptions.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -202,7 +202,7 @@ debug_loop:
ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
eret
exception_return
endfunc smc_handler64
unexpected_sync_exception:

4
bl2/aarch64/bl2_el3_entrypoint.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -95,5 +95,5 @@ func bl2_run_next_image
ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
eret
exception_return
endfunc bl2_run_next_image

2
bl31/aarch64/runtime_exceptions.S
View file

@ -456,7 +456,7 @@ smc_unknown:
smc_prohibited:
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
mov x0, #SMC_UNK
eret
exception_return
#if DEBUG
rt_svc_fw_critical_error:

4
bl32/tsp/aarch64/tsp_exceptions.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -64,7 +64,7 @@
smc #0
interrupt_exit_\label:
restore_caller_regs_and_lr
eret
exception_return
.endm
.globl tsp_exceptions

11
include/arch/aarch64/asm_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -218,4 +218,13 @@
ret
.endm
/*
* Macro for mitigating against speculative execution beyond ERET.
*/
.macro exception_return
eret
dsb nsh
isb
.endm
#endif /* ASM_MACROS_S */

4
lib/cpus/aarch64/cortex_a76.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -85,7 +85,7 @@
bic x3, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
csel x3, x3, x1, eq
msr CORTEX_A76_CPUACTLR2_EL1, x3
eret /* ERET implies ISB */
exception_return /* exception_return contains ISB */
.endif
1:
/*

4
lib/cpus/aarch64/neoverse_n1.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -553,7 +553,7 @@ func neoverse_n1_errata_ic_trap_handler
*/
esb
#endif
eret
exception_return
1:
ret
endfunc neoverse_n1_errata_ic_trap_handler

4
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -48,7 +48,7 @@ vector_base wa_cve_2017_5715_mmu_vbar
ccmp w0, w1, #0, eq
/* Static predictor will predict a fall through */
bne 1f
eret
exception_return
1:
.endif

2
lib/el3_runtime/aarch64/context.S
View file

@ -534,6 +534,6 @@ func el3_exit
*/
esb
#endif
eret
exception_return
endfunc el3_exit

4
plat/renesas/rcar/aarch64/plat_helpers.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -189,7 +189,7 @@ func bl2_enter_bl31
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
msr elr_el3, x0
msr spsr_el3, x1
eret
exception_return
endfunc bl2_enter_bl31
/* -----------------------------------------------------

4
services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -87,7 +87,7 @@ vector_entry SynchronousExceptionA64, .spm_shim_exceptions
do_smc:
mrs x30, tpidr_el1
smc #0
eret
exception_return
/* AArch64 system instructions trap are handled as a panic for now */
handle_sys_trap: