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f461fe346b
Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:679db7080129fb48ace43a08873eceabfd092aa1It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
162 lines
4 KiB
ArmAsm
162 lines
4 KiB
ArmAsm
/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl32/tsp/tsp.h>
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#include <common/bl_common.h>
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/* ----------------------------------------------------
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* The caller-saved registers x0-x18 and LR are saved
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* here.
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* ----------------------------------------------------
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*/
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#define SCRATCH_REG_SIZE #(20 * 8)
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.macro save_caller_regs_and_lr
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sub sp, sp, SCRATCH_REG_SIZE
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stp x0, x1, [sp]
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stp x2, x3, [sp, #0x10]
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stp x4, x5, [sp, #0x20]
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stp x6, x7, [sp, #0x30]
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stp x8, x9, [sp, #0x40]
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stp x10, x11, [sp, #0x50]
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stp x12, x13, [sp, #0x60]
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stp x14, x15, [sp, #0x70]
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stp x16, x17, [sp, #0x80]
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stp x18, x30, [sp, #0x90]
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.endm
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.macro restore_caller_regs_and_lr
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #0x10]
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ldp x4, x5, [sp, #0x20]
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ldp x6, x7, [sp, #0x30]
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ldp x8, x9, [sp, #0x40]
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ldp x10, x11, [sp, #0x50]
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ldp x12, x13, [sp, #0x60]
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ldp x14, x15, [sp, #0x70]
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ldp x16, x17, [sp, #0x80]
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ldp x18, x30, [sp, #0x90]
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add sp, sp, SCRATCH_REG_SIZE
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.endm
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/* ----------------------------------------------------
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* Common TSP interrupt handling routine
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* ----------------------------------------------------
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*/
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.macro handle_tsp_interrupt label
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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save_caller_regs_and_lr
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bl tsp_common_int_handler
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cbz x0, interrupt_exit_\label
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/*
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* This interrupt was not targetted to S-EL1 so send it to
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* the monitor and wait for execution to resume.
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*/
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smc #0
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interrupt_exit_\label:
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restore_caller_regs_and_lr
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exception_return
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.endm
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.globl tsp_exceptions
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/* -----------------------------------------------------
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* TSP exception handlers.
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* -----------------------------------------------------
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*/
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vector_base tsp_exceptions
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
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* are expected and treated as irrecoverable errors.
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_sp_el0
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b plat_panic_handler
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end_vector_entry sync_exception_sp_el0
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vector_entry irq_sp_el0
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b plat_panic_handler
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end_vector_entry irq_sp_el0
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vector_entry fiq_sp_el0
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b plat_panic_handler
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end_vector_entry fiq_sp_el0
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vector_entry serror_sp_el0
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b plat_panic_handler
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end_vector_entry serror_sp_el0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
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* are expected and handled
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_sp_elx
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b plat_panic_handler
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end_vector_entry sync_exception_sp_elx
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vector_entry irq_sp_elx
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handle_tsp_interrupt irq_sp_elx
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end_vector_entry irq_sp_elx
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vector_entry fiq_sp_elx
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handle_tsp_interrupt fiq_sp_elx
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end_vector_entry fiq_sp_elx
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vector_entry serror_sp_elx
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b plat_panic_handler
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end_vector_entry serror_sp_elx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
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* are handled since TSP does not implement a lower EL
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_aarch64
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b plat_panic_handler
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end_vector_entry sync_exception_aarch64
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vector_entry irq_aarch64
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b plat_panic_handler
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end_vector_entry irq_aarch64
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vector_entry fiq_aarch64
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b plat_panic_handler
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end_vector_entry fiq_aarch64
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vector_entry serror_aarch64
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b plat_panic_handler
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end_vector_entry serror_aarch64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800. No exceptions
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* handled since the TSP does not implement a lower EL.
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_aarch32
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b plat_panic_handler
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end_vector_entry sync_exception_aarch32
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vector_entry irq_aarch32
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b plat_panic_handler
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end_vector_entry irq_aarch32
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vector_entry fiq_aarch32
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b plat_panic_handler
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end_vector_entry fiq_aarch32
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vector_entry serror_aarch32
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b plat_panic_handler
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end_vector_entry serror_aarch32
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