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f461fe346b
Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:679db7080129fb48ace43a08873eceabfd092aa1It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
149 lines
4.2 KiB
ArmAsm
149 lines
4.2 KiB
ArmAsm
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <services/arm_arch_svc.h>
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.globl wa_cve_2017_5715_mmu_vbar
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#define ESR_EL3_A64_SMC0 0x5e000000
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#define ESR_EL3_A32_SMC0 0x4e000000
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vector_base wa_cve_2017_5715_mmu_vbar
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.macro apply_cve_2017_5715_wa _is_sync_exception _esr_el3_val
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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mrs x1, sctlr_el3
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/* Disable MMU */
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bic x1, x1, #SCTLR_M_BIT
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msr sctlr_el3, x1
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isb
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/* Enable MMU */
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orr x1, x1, #SCTLR_M_BIT
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msr sctlr_el3, x1
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/*
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* Defer ISB to avoid synchronizing twice in case we hit
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* the workaround SMC call which will implicitly synchronize
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* because of the ERET instruction.
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*/
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/*
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* Ensure SMC is coming from A64/A32 state on #0
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* with W0 = SMCCC_ARCH_WORKAROUND_1
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*
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* This sequence evaluates as:
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* (W0==SMCCC_ARCH_WORKAROUND_1) ? (ESR_EL3==SMC#0) : (NE)
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* allowing use of a single branch operation
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*/
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.if \_is_sync_exception
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orr w1, wzr, #SMCCC_ARCH_WORKAROUND_1
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cmp w0, w1
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mrs x0, esr_el3
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mov_imm w1, \_esr_el3_val
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ccmp w0, w1, #0, eq
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/* Static predictor will predict a fall through */
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bne 1f
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exception_return
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1:
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.endif
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/*
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* Synchronize now to enable the MMU. This is required
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* to ensure the load pair below reads the data stored earlier.
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*/
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isb
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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.endm
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_sp_el0
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b sync_exception_sp_el0
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end_vector_entry mmu_sync_exception_sp_el0
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vector_entry mmu_irq_sp_el0
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b irq_sp_el0
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end_vector_entry mmu_irq_sp_el0
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vector_entry mmu_fiq_sp_el0
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b fiq_sp_el0
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end_vector_entry mmu_fiq_sp_el0
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vector_entry mmu_serror_sp_el0
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b serror_sp_el0
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end_vector_entry mmu_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_sp_elx
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b sync_exception_sp_elx
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end_vector_entry mmu_sync_exception_sp_elx
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vector_entry mmu_irq_sp_elx
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b irq_sp_elx
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end_vector_entry mmu_irq_sp_elx
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vector_entry mmu_fiq_sp_elx
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b fiq_sp_elx
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end_vector_entry mmu_fiq_sp_elx
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vector_entry mmu_serror_sp_elx
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b serror_sp_elx
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end_vector_entry mmu_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0
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b sync_exception_aarch64
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end_vector_entry mmu_sync_exception_aarch64
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vector_entry mmu_irq_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b irq_aarch64
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end_vector_entry mmu_irq_aarch64
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vector_entry mmu_fiq_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b fiq_aarch64
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end_vector_entry mmu_fiq_aarch64
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vector_entry mmu_serror_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b serror_aarch64
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end_vector_entry mmu_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0
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b sync_exception_aarch32
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end_vector_entry mmu_sync_exception_aarch32
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vector_entry mmu_irq_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b irq_aarch32
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end_vector_entry mmu_irq_aarch32
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vector_entry mmu_fiq_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b fiq_aarch32
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end_vector_entry mmu_fiq_aarch32
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vector_entry mmu_serror_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b serror_aarch32
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end_vector_entry mmu_serror_aarch32
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