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Remove coherent memory from the BL memory maps
This patch extends the build option `USE_COHERENT_MEMORY` to conditionally remove coherent memory from the memory maps of all boot loader stages. The patch also adds necessary documentation for coherent memory removal in firmware-design, porting and user guides. Fixes ARM-Software/tf-issues#106 Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
This commit is contained in:
Soby Mathew
Dan Handley
parent
8c5fe0b5b9
commit
ab8707e687
26 changed files with 463 additions and 87 deletions
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@ -131,9 +131,11 @@ func bl1_entrypoint
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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#endif
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ldr x0, =__DATA_RAM_START__
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ldr x1, =__DATA_ROM_START__
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@ -107,6 +107,7 @@ SECTIONS
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*(xlat_table)
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} >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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@ -125,6 +126,7 @@ SECTIONS
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. = NEXT(4096);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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__BL1_RAM_START__ = ADDR(.data);
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__BL1_RAM_END__ = .;
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@ -140,8 +142,10 @@ SECTIONS
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif
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ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
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}
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@ -91,9 +91,11 @@ func bl2_entrypoint
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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#endif
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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@ -93,6 +93,7 @@ SECTIONS
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*(xlat_table)
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} >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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@ -111,12 +112,16 @@ SECTIONS
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. = NEXT(4096);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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__BL2_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif
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ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
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}
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@ -149,9 +149,11 @@ func bl31_entrypoint
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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#endif
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/* ---------------------------------------------
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* Initialize the cpu_ops pointer.
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@ -117,6 +117,7 @@ SECTIONS
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*(xlat_table)
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} >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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@ -135,12 +136,15 @@ SECTIONS
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. = NEXT(4096);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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__BL31_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif
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ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
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}
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@ -108,9 +108,11 @@ func tsp_entrypoint
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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#endif
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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@ -98,6 +98,7 @@ SECTIONS
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*(xlat_table)
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} >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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@ -116,12 +117,15 @@ SECTIONS
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. = NEXT(4096);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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__BL32_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif
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ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.")
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}
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@ -43,7 +43,7 @@
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* of trusted SRAM
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******************************************************************************/
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extern unsigned long __RO_START__;
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extern unsigned long __COHERENT_RAM_END__;
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extern unsigned long __BL32_END__;
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/*******************************************************************************
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* Lock to control access to the console
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@ -63,11 +63,11 @@ work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* The BL32 memory footprint starts with an RO sections and ends
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* with a section for coherent RAM. Use it to find the memory size
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* with the linker symbol __BL32_END__. Use it to find the memory size
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******************************************************************************/
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#define BL32_TOTAL_BASE (unsigned long)(&__RO_START__)
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#define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__)
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static tsp_args_t *set_smc_args(uint64_t arg0,
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uint64_t arg1,
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@ -12,8 +12,9 @@ Contents :
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7. [CPU specific operations framework](#7--cpu-specific-operations-framework)
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8. [Memory layout of BL images](#8-memory-layout-of-bl-images)
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9. [Firmware Image Package (FIP)](#9--firmware-image-package-fip)
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10. [Code Structure](#10--code-structure)
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11. [References](#11--references)
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10. [Use of coherent memory in Trusted Firmware](#10--use-of-coherent-memory-in-trusted-firmware)
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11. [Code Structure](#11--code-structure)
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12. [References](#12--references)
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1. Introduction
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@ -368,10 +369,10 @@ level implementation of the generic timer through the memory mapped interface.
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`ON`; any other cluster is `OFF`. BL3-1 initializes the data structures that
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implement the state machine, including the locks that protect them. BL3-1
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accesses the state of a CPU or cluster immediately after reset and before
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the MMU is enabled in the warm boot path. It is not currently possible to
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use 'exclusive' based spinlocks, therefore BL3-1 uses locks based on
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Lamport's Bakery algorithm instead. BL3-1 allocates these locks in device
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memory. They are accessible irrespective of MMU state.
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the data cache is enabled in the warm boot path. It is not currently
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possible to use 'exclusive' based spinlocks, therefore BL3-1 uses locks
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based on Lamport's Bakery algorithm instead. BL3-1 allocates these locks in
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device memory by default.
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* Runtime services initialization:
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@ -1127,9 +1128,10 @@ this purpose:
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* `__BSS_START__` This address must be aligned on a 16-byte boundary.
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* `__BSS_SIZE__`
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Similarly, the coherent memory section must be zero-initialised. Also, the MMU
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setup code needs to know the extents of this section to set the right memory
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attributes for it. The following linker symbols are defined for this purpose:
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Similarly, the coherent memory section (if enabled) must be zero-initialised.
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Also, the MMU setup code needs to know the extents of this section to set the
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right memory attributes for it. The following linker symbols are defined for
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this purpose:
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* `__COHERENT_RAM_START__` This address must be aligned on a page-size boundary.
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* `__COHERENT_RAM_END__` This address must be aligned on a page-size boundary.
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@ -1443,7 +1445,208 @@ Currently the FVP's policy only allows loading of a known set of images. The
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platform policy can be modified to allow additional images.
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10. Code Structure
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10. Use of coherent memory in Trusted Firmware
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----------------------------------------------
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There might be loss of coherency when physical memory with mismatched
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shareability, cacheability and memory attributes is accessed by multiple CPUs
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(refer to section B2.9 of [ARM ARM] for more details). This possibility occurs
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in Trusted Firmware during power up/down sequences when coherency, MMU and
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caches are turned on/off incrementally.
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Trusted Firmware defines coherent memory as a region of memory with Device
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nGnRE attributes in the translation tables. The translation granule size in
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Trusted Firmware is 4KB. This is the smallest possible size of the coherent
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memory region.
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By default, all data structures which are susceptible to accesses with
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mismatched attributes from various CPUs are allocated in a coherent memory
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region (refer to section 2.1 of [Porting Guide]). The coherent memory region
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accesses are Outer Shareable, non-cacheable and they can be accessed
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with the Device nGnRE attributes when the MMU is turned on. Hence, at the
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expense of at least an extra page of memory, Trusted Firmware is able to work
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around coherency issues due to mismatched memory attributes.
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The alternative to the above approach is to allocate the susceptible data
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structures in Normal WriteBack WriteAllocate Inner shareable memory. This
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approach requires the data structures to be designed so that it is possible to
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work around the issue of mismatched memory attributes by performing software
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cache maintenance on them.
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### Disabling the use of coherent memory in Trusted Firmware
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It might be desirable to avoid the cost of allocating coherent memory on
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platforms which are memory constrained. Trusted Firmware enables inclusion of
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coherent memory in firmware images through the build flag `USE_COHERENT_MEM`.
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This flag is enabled by default. It can be disabled to choose the second
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approach described above.
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The below sections analyze the data structures allocated in the coherent memory
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region and the changes required to allocate them in normal memory.
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### PSCI Affinity map nodes
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The `psci_aff_map` data structure stores the hierarchial node information for
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each affinity level in the system including the PSCI states associated with them.
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By default, this data structure is allocated in the coherent memory region in
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the Trusted Firmware because it can be accessed by multiple CPUs, either with
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their caches enabled or disabled.
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typedef struct aff_map_node {
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unsigned long mpidr;
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unsigned char ref_count;
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unsigned char state;
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unsigned char level;
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#if USE_COHERENT_MEM
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bakery_lock_t lock;
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#else
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unsigned char aff_map_index;
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#endif
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} aff_map_node_t;
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In order to move this data structure to normal memory, the use of each of its
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fields must be analyzed. Fields like `mpidr` and `level` are only written once
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during cold boot. Hence removing them from coherent memory involves only doing
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a clean and invalidate of the cache lines after these fields are written.
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The fields `state` and `ref_count` can be concurrently accessed by multiple
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CPUs in different cache states. A Lamport's Bakery lock is used to ensure mutual
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exlusion to these fields. As a result, it is possible to move these fields out
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of coherent memory by performing software cache maintenance on them. The field
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`lock` is the bakery lock data structure when `USE_COHERENT_MEM` is enabled.
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The `aff_map_index` is used to identify the bakery lock when `USE_COHERENT_MEM`
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is disabled.
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### Bakery lock data
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The bakery lock data structure `bakery_lock_t` is allocated in coherent memory
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and is accessed by multiple CPUs with mismatched attributes. `bakery_lock_t` is
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defined as follows:
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typedef struct bakery_lock {
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int owner;
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volatile char entering[BAKERY_LOCK_MAX_CPUS];
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volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
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} bakery_lock_t;
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It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
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fields can be read by all CPUs but only written to by the owning CPU.
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Depending upon the data cache line size, the per-CPU fields of the
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`bakery_lock_t` structure for multiple CPUs may exist on a single cache line.
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These per-CPU fields can be read and written during lock contention by multiple
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CPUs with mismatched memory attributes. Since these fields are a part of the
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lock implementation, they do not have access to any other locking primitive to
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safeguard against the resulting coherency issues. As a result, simple software
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cache maintenance is not enough to allocate them in coherent memory. Consider
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the following example.
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CPU0 updates its per-CPU field with data cache enabled. This write updates a
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local cache line which contains a copy of the fields for other CPUs as well. Now
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CPU1 updates its per-CPU field of the `bakery_lock_t` structure with data cache
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disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
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its field in any other cache line in the system. This operation will invalidate
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the update made by CPU0 as well.
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To use bakery locks when `USE_COHERENT_MEM` is disabled, the lock data structure
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has been redesigned. The changes utilise the characteristic of Lamport's Bakery
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algorithm mentioned earlier. The per-CPU fields of the new lock structure are
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aligned such that they are allocated on separate cache lines. The per-CPU data
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framework in Trusted Firmware is used to achieve this. This enables software to
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perform software cache maintenance on the lock data structure without running
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into coherency issues associated with mismatched attributes.
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The per-CPU data framework enables consolidation of data structures on the
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fewest cache lines possible. This saves memory as compared to the scenario where
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each data structure is separately aligned to the cache line boundary to achieve
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the same effect.
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The bakery lock data structure `bakery_info_t` is defined for use when
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`USE_COHERENT_MEM` is disabled as follows:
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typedef struct bakery_info {
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/*
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* The lock_data is a bit-field of 2 members:
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* Bit[0] : choosing. This field is set when the CPU is
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* choosing its bakery number.
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* Bits[1 - 15] : number. This is the bakery number allocated.
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*/
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volatile uint16_t lock_data;
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} bakery_info_t;
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The `bakery_info_t` represents a single per-CPU field of one lock and
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the combination of corresponding `bakery_info_t` structures for all CPUs in the
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system represents the complete bakery lock. It is embedded in the per-CPU
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data framework `cpu_data` as shown below:
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CPU0 cpu_data
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------------------
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| .... |
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|----------------|
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| `bakery_info_t`| <-- Lock_0 per-CPU field
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| Lock_0 | for CPU0
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|----------------|
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| `bakery_info_t`| <-- Lock_1 per-CPU field
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| Lock_1 | for CPU0
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|----------------|
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| .... |
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|----------------|
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| `bakery_info_t`| <-- Lock_N per-CPU field
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| Lock_N | for CPU0
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------------------
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CPU1 cpu_data
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------------------
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| .... |
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|----------------|
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| `bakery_info_t`| <-- Lock_0 per-CPU field
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| Lock_0 | for CPU1
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|----------------|
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| `bakery_info_t`| <-- Lock_1 per-CPU field
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| Lock_1 | for CPU1
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|----------------|
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| .... |
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|----------------|
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| `bakery_info_t`| <-- Lock_N per-CPU field
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| Lock_N | for CPU1
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------------------
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Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
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operation on Lock_N, the corresponding `bakery_info_t` in both CPU0 and CPU1
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`cpu_data` need to be fetched and appropriate cache operations need to be
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performed for each access.
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For multiple bakery locks, an array of `bakery_info_t` is declared in `cpu_data`
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and each lock is given an `id` to identify it in the array.
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### Non Functional Impact of removing coherent memory
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Removal of the coherent memory region leads to the additional software overhead
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of performing cache maintenance for the affected data structures. However, since
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the memory where the data structures are allocated is cacheable, the overhead is
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mostly mitigated by an increase in performance.
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There is however a performance impact for bakery locks, due to:
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* Additional cache maintenance operations, and
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* Multiple cache line reads for each lock operation, since the bakery locks
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for each CPU are distributed across different cache lines.
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The implementation has been optimized to mimimize this additional overhead.
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Measurements indicate that when bakery locks are allocated in Normal memory, the
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minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
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in Device memory the same is 2 micro seconds. The measurements were done on the
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Juno ARM development platform.
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As mentioned earlier, almost a page of memory can be saved by disabling
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`USE_COHERENT_MEM`. Each platform needs to consider these trade-offs to decide
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whether coherent memory should be used. If a platform disables
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`USE_COHERENT_MEM` and needs to use bakery locks in the porting layer, it should
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reserve memory in `cpu_data` by defining the macro `PLAT_PCPU_DATA_SIZE` (see
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the [Porting Guide]). Refer to the reference platform code for examples.
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11. Code Structure
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-------------------
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Trusted Firmware code is logically divided between the three boot loader
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|
|
@ -1488,7 +1691,7 @@ FDTs provide a description of the hardware platform and are used by the Linux
|
|||
kernel at boot time. These can be found in the `fdts` directory.
|
||||
|
||||
|
||||
11. References
|
||||
12. References
|
||||
---------------
|
||||
|
||||
1. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available
|
||||
|
|
@ -1504,7 +1707,7 @@ kernel at boot time. These can be found in the `fdts` directory.
|
|||
|
||||
_Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
|
||||
|
||||
|
||||
[ARM ARM]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html "ARMv8-A Reference Manual (ARM DDI0487A.E)"
|
||||
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022b/index.html "Power State Coordination Interface PDD (ARM DEN 0022B.b)"
|
||||
[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)"
|
||||
[UUID]: https://tools.ietf.org/rfc/rfc4122.txt "A Universally Unique IDentifier (UUID) URN Namespace"
|
||||
|
|
|
|||
|
|
@ -63,11 +63,11 @@ mapped page tables, and enable both the instruction and data caches for each BL
|
|||
stage. In the ARM FVP port, each BL stage configures the MMU in its platform-
|
||||
specific architecture setup function, for example `blX_plat_arch_setup()`.
|
||||
|
||||
Each platform must allocate a block of identity mapped secure memory with
|
||||
Device-nGnRE attributes aligned to page boundary (4K) for each BL stage. This
|
||||
memory is identified by the section name `tzfw_coherent_mem` so that its
|
||||
possible for the firmware to place variables in it using the following C code
|
||||
directive:
|
||||
If the build option `USE_COHERENT_MEM` is enabled, each platform must allocate a
|
||||
block of identity mapped secure memory with Device-nGnRE attributes aligned to
|
||||
page boundary (4K) for each BL stage. This memory is identified by the section
|
||||
name `tzfw_coherent_mem` so that its possible for the firmware to place
|
||||
variables in it using the following C code directive:
|
||||
|
||||
__attribute__ ((section("tzfw_coherent_mem")))
|
||||
|
||||
|
|
@ -246,6 +246,17 @@ must also be defined:
|
|||
entities than this value using `io_open()` will fail with
|
||||
IO_RESOURCES_EXHAUSTED.
|
||||
|
||||
If the platform needs to allocate data within the per-cpu data framework in
|
||||
BL3-1, it should define the following macro. Currently this is only required if
|
||||
the platform decides not to use the coherent memory section by undefining the
|
||||
USE_COHERENT_MEM build flag. In this case, the framework allocates the required
|
||||
memory within the the per-cpu data to minimize wastage.
|
||||
|
||||
* **#define : PLAT_PCPU_DATA_SIZE**
|
||||
|
||||
Defines the memory (in bytes) to be reserved within the per-cpu data
|
||||
structure for use by the platform layer.
|
||||
|
||||
The following constants are optional. They should be defined when the platform
|
||||
memory layout implies some image overlaying like on FVP.
|
||||
|
||||
|
|
|
|||
|
|
@ -245,6 +245,12 @@ performed.
|
|||
synchronous method) or 1 (BL3-2 is initialized using asynchronous method).
|
||||
Default is 0.
|
||||
|
||||
* `USE_COHERENT_MEM`: This flag determines whether to include the coherent
|
||||
memory region in the BL memory map or not (see "Use of Coherent memory in
|
||||
Trusted Firmware" section in [Firmware Design]). It can take the value 1
|
||||
(Coherent memory region is included) or 0 (Coherent memory region is
|
||||
excluded). Default is 1.
|
||||
|
||||
#### FVP specific build options
|
||||
|
||||
* `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options:
|
||||
|
|
|
|||
|
|
@ -136,7 +136,8 @@ const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
|
|||
* Macro generating the code for the function setting up the pagetables as per
|
||||
* the platform memory map & initialize the mmu, for the given exception level
|
||||
******************************************************************************/
|
||||
#define DEFINE_CONFIGURE_MMU_EL(_el) \
|
||||
#if USE_COHERENT_MEM
|
||||
#define DEFINE_CONFIGURE_MMU_EL(_el) \
|
||||
void fvp_configure_mmu_el##_el(unsigned long total_base, \
|
||||
unsigned long total_size, \
|
||||
unsigned long ro_start, \
|
||||
|
|
@ -158,6 +159,25 @@ const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
|
|||
\
|
||||
enable_mmu_el##_el(0); \
|
||||
}
|
||||
#else
|
||||
#define DEFINE_CONFIGURE_MMU_EL(_el) \
|
||||
void fvp_configure_mmu_el##_el(unsigned long total_base, \
|
||||
unsigned long total_size, \
|
||||
unsigned long ro_start, \
|
||||
unsigned long ro_limit) \
|
||||
{ \
|
||||
mmap_add_region(total_base, total_base, \
|
||||
total_size, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE); \
|
||||
mmap_add_region(ro_start, ro_start, \
|
||||
ro_limit - ro_start, \
|
||||
MT_MEMORY | MT_RO | MT_SECURE); \
|
||||
mmap_add(fvp_mmap); \
|
||||
init_xlat_tables(); \
|
||||
\
|
||||
enable_mmu_el##_el(0); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Define EL1 and EL3 variants of the function initialising the MMU */
|
||||
DEFINE_CONFIGURE_MMU_EL(1)
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
#include "fvp_def.h"
|
||||
#include "fvp_private.h"
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*******************************************************************************
|
||||
* Declarations of linker defined symbols which will help us find the layout
|
||||
* of trusted SRAM
|
||||
|
|
@ -56,6 +57,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
#endif
|
||||
|
||||
/* Data structure which holds the extents of the trusted SRAM for BL1*/
|
||||
static meminfo_t bl1_tzram_layout;
|
||||
|
|
@ -116,9 +118,12 @@ void bl1_plat_arch_setup(void)
|
|||
fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
|
||||
bl1_tzram_layout.total_size,
|
||||
BL1_RO_BASE,
|
||||
BL1_RO_LIMIT,
|
||||
BL1_COHERENT_RAM_BASE,
|
||||
BL1_COHERENT_RAM_LIMIT);
|
||||
BL1_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
, BL1_COHERENT_RAM_BASE,
|
||||
BL1_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -45,8 +45,10 @@
|
|||
extern unsigned long __RO_START__;
|
||||
extern unsigned long __RO_END__;
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
extern unsigned long __COHERENT_RAM_START__;
|
||||
extern unsigned long __COHERENT_RAM_END__;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the code & RO data region.
|
||||
|
|
@ -57,6 +59,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
|
||||
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
|
|
@ -66,11 +69,11 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
#endif
|
||||
|
||||
/* Data structure which holds the extents of the trusted SRAM for BL2 */
|
||||
static meminfo_t bl2_tzram_layout
|
||||
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
|
||||
section("tzfw_coherent_mem")));
|
||||
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE)));
|
||||
|
||||
/* Assert that BL3-1 parameters fit in shared memory */
|
||||
CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) <
|
||||
|
|
@ -209,9 +212,12 @@ void bl2_plat_arch_setup(void)
|
|||
fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
|
||||
bl2_tzram_layout.total_size,
|
||||
BL2_RO_BASE,
|
||||
BL2_RO_LIMIT,
|
||||
BL2_COHERENT_RAM_BASE,
|
||||
BL2_COHERENT_RAM_LIMIT);
|
||||
BL2_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
, BL2_COHERENT_RAM_BASE,
|
||||
BL2_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -48,19 +48,25 @@
|
|||
******************************************************************************/
|
||||
extern unsigned long __RO_START__;
|
||||
extern unsigned long __RO_END__;
|
||||
extern unsigned long __BL31_END__;
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
extern unsigned long __COHERENT_RAM_START__;
|
||||
extern unsigned long __COHERENT_RAM_END__;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the code & RO data region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
* page-aligned. It is the responsibility of the linker script to ensure that
|
||||
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
|
||||
* The next 3 constants identify the extents of the code, RO data region and the
|
||||
* limit of the BL3-1 image. These addresses are used by the MMU setup code and
|
||||
* therefore they must be page-aligned. It is the responsibility of the linker
|
||||
* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
|
||||
* refer to page-aligned addresses.
|
||||
*/
|
||||
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
|
||||
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
|
||||
#define BL31_END (unsigned long)(&__BL31_END__)
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
|
|
@ -70,7 +76,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
|
||||
#endif
|
||||
|
||||
#if RESET_TO_BL31
|
||||
static entry_point_info_t bl32_image_ep_info;
|
||||
|
|
@ -235,9 +241,12 @@ void bl31_plat_arch_setup(void)
|
|||
fvp_cci_enable();
|
||||
#endif
|
||||
fvp_configure_mmu_el3(BL31_RO_BASE,
|
||||
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
|
||||
(BL31_END - BL31_RO_BASE),
|
||||
BL31_RO_BASE,
|
||||
BL31_RO_LIMIT,
|
||||
BL31_COHERENT_RAM_BASE,
|
||||
BL31_COHERENT_RAM_LIMIT);
|
||||
BL31_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
, BL31_COHERENT_RAM_BASE,
|
||||
BL31_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -118,15 +118,21 @@ CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(fvp_cpu_data_t), \
|
|||
void fvp_configure_mmu_el1(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long,
|
||||
unsigned long,
|
||||
unsigned long,
|
||||
unsigned long);
|
||||
unsigned long
|
||||
#if USE_COHERENT_MEM
|
||||
, unsigned long,
|
||||
unsigned long
|
||||
#endif
|
||||
);
|
||||
void fvp_configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long,
|
||||
unsigned long,
|
||||
unsigned long,
|
||||
unsigned long);
|
||||
unsigned long
|
||||
#if USE_COHERENT_MEM
|
||||
, unsigned long,
|
||||
unsigned long
|
||||
#endif
|
||||
);
|
||||
|
||||
int fvp_config_setup(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -40,19 +40,25 @@
|
|||
******************************************************************************/
|
||||
extern unsigned long __RO_START__;
|
||||
extern unsigned long __RO_END__;
|
||||
extern unsigned long __BL32_END__;
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
extern unsigned long __COHERENT_RAM_START__;
|
||||
extern unsigned long __COHERENT_RAM_END__;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the code & RO data region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
* page-aligned. It is the responsibility of the linker script to ensure that
|
||||
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
|
||||
* The next 3 constants identify the extents of the code & RO data region and
|
||||
* the limit of the BL3-2 image. These addresses are used by the MMU setup code
|
||||
* and therefore they must be page-aligned. It is the responsibility of the
|
||||
* linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__
|
||||
* linker symbols refer to page-aligned addresses.
|
||||
*/
|
||||
#define BL32_RO_BASE (unsigned long)(&__RO_START__)
|
||||
#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
|
||||
#define BL32_END (unsigned long)(&__BL32_END__)
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
|
|
@ -62,6 +68,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the UART
|
||||
|
|
@ -93,9 +100,12 @@ void tsp_platform_setup(void)
|
|||
void tsp_plat_arch_setup(void)
|
||||
{
|
||||
fvp_configure_mmu_el1(BL32_RO_BASE,
|
||||
(BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
|
||||
(BL32_END - BL32_RO_BASE),
|
||||
BL32_RO_BASE,
|
||||
BL32_RO_LIMIT,
|
||||
BL32_COHERENT_RAM_BASE,
|
||||
BL32_COHERENT_RAM_LIMIT);
|
||||
BL32_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
, BL32_COHERENT_RAM_BASE,
|
||||
BL32_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@ const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
|
|||
* Macro generating the code for the function setting up the pagetables as per
|
||||
* the platform memory map & initialize the mmu, for the given exception level
|
||||
******************************************************************************/
|
||||
#if USE_COHERENT_MEM
|
||||
#define DEFINE_CONFIGURE_MMU_EL(_el) \
|
||||
void configure_mmu_el##_el(unsigned long total_base, \
|
||||
unsigned long total_size, \
|
||||
|
|
@ -162,7 +163,25 @@ const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
|
|||
\
|
||||
enable_mmu_el##_el(0); \
|
||||
}
|
||||
|
||||
#else
|
||||
#define DEFINE_CONFIGURE_MMU_EL(_el) \
|
||||
void configure_mmu_el##_el(unsigned long total_base, \
|
||||
unsigned long total_size, \
|
||||
unsigned long ro_start, \
|
||||
unsigned long ro_limit) \
|
||||
{ \
|
||||
mmap_add_region(total_base, total_base, \
|
||||
total_size, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE); \
|
||||
mmap_add_region(ro_start, ro_start, \
|
||||
ro_limit - ro_start, \
|
||||
MT_MEMORY | MT_RO | MT_SECURE); \
|
||||
mmap_add(juno_mmap); \
|
||||
init_xlat_tables(); \
|
||||
\
|
||||
enable_mmu_el##_el(0); \
|
||||
}
|
||||
#endif
|
||||
/* Define EL1 and EL3 variants of the function initialising the MMU */
|
||||
DEFINE_CONFIGURE_MMU_EL(1)
|
||||
DEFINE_CONFIGURE_MMU_EL(3)
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#include "juno_def.h"
|
||||
#include "juno_private.h"
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*******************************************************************************
|
||||
* Declarations of linker defined symbols which will help us find the layout
|
||||
* of trusted RAM
|
||||
|
|
@ -57,6 +58,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
#endif
|
||||
|
||||
/* Data structure which holds the extents of the trusted RAM for BL1 */
|
||||
static meminfo_t bl1_tzram_layout;
|
||||
|
|
@ -189,9 +191,12 @@ void bl1_plat_arch_setup(void)
|
|||
configure_mmu_el3(bl1_tzram_layout.total_base,
|
||||
bl1_tzram_layout.total_size,
|
||||
TZROM_BASE,
|
||||
TZROM_BASE + TZROM_SIZE,
|
||||
BL1_COHERENT_RAM_BASE,
|
||||
BL1_COHERENT_RAM_LIMIT);
|
||||
TZROM_BASE + TZROM_SIZE
|
||||
#if USE_COHERENT_MEM
|
||||
, BL1_COHERENT_RAM_BASE,
|
||||
BL1_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -47,8 +47,10 @@
|
|||
extern unsigned long __RO_START__;
|
||||
extern unsigned long __RO_END__;
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
extern unsigned long __COHERENT_RAM_START__;
|
||||
extern unsigned long __COHERENT_RAM_END__;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the code & RO data region.
|
||||
|
|
@ -59,6 +61,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
|
||||
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
|
|
@ -68,11 +71,11 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
#endif
|
||||
|
||||
/* Data structure which holds the extents of the trusted RAM for BL2 */
|
||||
static meminfo_t bl2_tzram_layout
|
||||
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
|
||||
section("tzfw_coherent_mem")));
|
||||
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE)));
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure which holds the arguments which need to be passed to BL3-1
|
||||
|
|
@ -194,9 +197,12 @@ void bl2_plat_arch_setup(void)
|
|||
configure_mmu_el1(bl2_tzram_layout.total_base,
|
||||
bl2_tzram_layout.total_size,
|
||||
BL2_RO_BASE,
|
||||
BL2_RO_LIMIT,
|
||||
BL2_COHERENT_RAM_BASE,
|
||||
BL2_COHERENT_RAM_LIMIT);
|
||||
BL2_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
, BL2_COHERENT_RAM_BASE,
|
||||
BL2_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -48,19 +48,25 @@
|
|||
******************************************************************************/
|
||||
extern unsigned long __RO_START__;
|
||||
extern unsigned long __RO_END__;
|
||||
extern unsigned long __BL31_END__;
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
extern unsigned long __COHERENT_RAM_START__;
|
||||
extern unsigned long __COHERENT_RAM_END__;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the code & RO data region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
* page-aligned. It is the responsibility of the linker script to ensure that
|
||||
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
|
||||
* The next 3 constants identify the extents of the code, RO data region and the
|
||||
* limit of the BL3-1 image. These addresses are used by the MMU setup code and
|
||||
* therefore they must be page-aligned. It is the responsibility of the linker
|
||||
* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
|
||||
* refer to page-aligned addresses.
|
||||
*/
|
||||
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
|
||||
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
|
||||
#define BL31_END (unsigned long)(&__BL31_END__)
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
|
|
@ -70,6 +76,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
* Placeholder variables for copying the arguments that have been passed to
|
||||
|
|
@ -178,9 +185,13 @@ void bl31_platform_setup(void)
|
|||
void bl31_plat_arch_setup()
|
||||
{
|
||||
configure_mmu_el3(BL31_RO_BASE,
|
||||
BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE,
|
||||
(BL31_END - BL31_RO_BASE),
|
||||
BL31_RO_BASE,
|
||||
BL31_RO_LIMIT,
|
||||
BL31_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
,
|
||||
BL31_COHERENT_RAM_BASE,
|
||||
BL31_COHERENT_RAM_LIMIT);
|
||||
BL31_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -134,15 +134,21 @@ unsigned int platform_get_core_pos(unsigned long mpidr);
|
|||
void configure_mmu_el1(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
unsigned long ro_limit
|
||||
#if USE_COHERENT_MEM
|
||||
, unsigned long coh_start,
|
||||
unsigned long coh_limit
|
||||
#endif
|
||||
);
|
||||
void configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
unsigned long ro_limit
|
||||
#if USE_COHERENT_MEM
|
||||
, unsigned long coh_start,
|
||||
unsigned long coh_limit
|
||||
#endif
|
||||
);
|
||||
void plat_report_exception(unsigned long type);
|
||||
unsigned long plat_get_ns_image_entrypoint(void);
|
||||
unsigned long platform_get_stack(unsigned long mpidr);
|
||||
|
|
|
|||
|
|
@ -40,19 +40,25 @@
|
|||
******************************************************************************/
|
||||
extern unsigned long __RO_START__;
|
||||
extern unsigned long __RO_END__;
|
||||
extern unsigned long __BL32_END__;
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
extern unsigned long __COHERENT_RAM_START__;
|
||||
extern unsigned long __COHERENT_RAM_END__;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the code & RO data region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
* page-aligned. It is the responsibility of the linker script to ensure that
|
||||
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
|
||||
* The next 3 constants identify the extents of the code, RO data region and the
|
||||
* limit of the BL3-2 image. These addresses are used by the MMU setup code and
|
||||
* therefore they must be page-aligned. It is the responsibility of the linker
|
||||
* script to ensure that __RO_START__, __RO_END__ & __BL32_END__ linker symbols
|
||||
* refer to page-aligned addresses.
|
||||
*/
|
||||
#define BL32_RO_BASE (unsigned long)(&__RO_START__)
|
||||
#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
|
||||
#define BL32_END (unsigned long)(&__BL32_END__)
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
|
|
@ -62,6 +68,7 @@ extern unsigned long __COHERENT_RAM_END__;
|
|||
*/
|
||||
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the UART
|
||||
|
|
@ -90,9 +97,12 @@ void tsp_platform_setup(void)
|
|||
void tsp_plat_arch_setup(void)
|
||||
{
|
||||
configure_mmu_el1(BL32_RO_BASE,
|
||||
BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE,
|
||||
(BL32_END - BL32_RO_BASE),
|
||||
BL32_RO_BASE,
|
||||
BL32_RO_LIMIT,
|
||||
BL32_COHERENT_RAM_BASE,
|
||||
BL32_COHERENT_RAM_LIMIT);
|
||||
BL32_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
, BL32_COHERENT_RAM_BASE,
|
||||
BL32_COHERENT_RAM_LIMIT
|
||||
#endif
|
||||
);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,10 @@ const spd_pm_ops_t *psci_spd_pm;
|
|||
* corresponds to an affinity instance e.g. cluster, cpu within an mpidr
|
||||
******************************************************************************/
|
||||
aff_map_node_t psci_aff_map[PSCI_NUM_AFFS]
|
||||
__attribute__ ((section("tzfw_coherent_mem")));
|
||||
#if USE_COHERENT_MEM
|
||||
__attribute__ ((section("tzfw_coherent_mem")))
|
||||
#endif
|
||||
;
|
||||
|
||||
/*******************************************************************************
|
||||
* Pointer to functions exported by the platform to complete power mgmt. ops
|
||||
|
|
@ -352,6 +355,10 @@ int psci_save_ns_entry(uint64_t mpidr,
|
|||
******************************************************************************/
|
||||
unsigned short psci_get_state(aff_map_node_t *node)
|
||||
{
|
||||
#if !USE_COHERENT_MEM
|
||||
flush_dcache_range((uint64_t) node, sizeof(*node));
|
||||
#endif
|
||||
|
||||
assert(node->level >= MPIDR_AFFLVL0 && node->level <= MPIDR_MAX_AFFLVL);
|
||||
|
||||
/* A cpu node just contains the state which can be directly returned */
|
||||
|
|
@ -409,6 +416,10 @@ void psci_set_state(aff_map_node_t *node, unsigned short state)
|
|||
node->state &= ~(PSCI_STATE_MASK << PSCI_STATE_SHIFT);
|
||||
node->state |= (state & PSCI_STATE_MASK) << PSCI_STATE_SHIFT;
|
||||
}
|
||||
|
||||
#if !USE_COHERENT_MEM
|
||||
flush_dcache_range((uint64_t) node, sizeof(*node));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -331,13 +331,20 @@ int32_t psci_setup(void)
|
|||
afflvl);
|
||||
}
|
||||
|
||||
#if !USE_COHERENT_MEM
|
||||
/*
|
||||
* The psci_aff_map only needs flushing when it's not allocated in
|
||||
* coherent memory.
|
||||
*/
|
||||
flush_dcache_range((uint64_t) &psci_aff_map, sizeof(psci_aff_map));
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set the bounds for the affinity counts of each level in the map. Also
|
||||
* flush out the entire array so that it's visible to subsequent power
|
||||
* management operations. The 'psci_aff_map' array is allocated in
|
||||
* coherent memory so does not need flushing. The 'psci_aff_limits'
|
||||
* array is allocated in normal memory. It will be accessed when the mmu
|
||||
* is off e.g. after reset. Hence it needs to be flushed.
|
||||
* management operations. The 'psci_aff_limits' array is allocated in
|
||||
* normal memory. It will be accessed when the mmu is off e.g. after
|
||||
* reset. Hence it needs to be flushed.
|
||||
*/
|
||||
for (afflvl = MPIDR_AFFLVL0; afflvl < max_afflvl; afflvl++) {
|
||||
psci_aff_limits[afflvl].min =
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue