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ab8707e687
This patch extends the build option `USE_COHERENT_MEMORY` to conditionally remove coherent memory from the memory maps of all boot loader stages. The patch also adds necessary documentation for coherent memory removal in firmware-design, porting and user guides. Fixes ARM-Software/tf-issues#106 Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
108 lines
4.3 KiB
C
108 lines
4.3 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bl_common.h>
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#include <console.h>
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#include <platform_tsp.h>
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#include "../juno_def.h"
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#include "../juno_private.h"
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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extern unsigned long __RO_START__;
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extern unsigned long __RO_END__;
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extern unsigned long __BL32_END__;
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#if USE_COHERENT_MEM
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extern unsigned long __COHERENT_RAM_START__;
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extern unsigned long __COHERENT_RAM_END__;
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#endif
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/*
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* The next 3 constants identify the extents of the code, RO data region and the
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* limit of the BL3-2 image. These addresses are used by the MMU setup code and
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* therefore they must be page-aligned. It is the responsibility of the linker
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* script to ensure that __RO_START__, __RO_END__ & __BL32_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL32_RO_BASE (unsigned long)(&__RO_START__)
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#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL32_END (unsigned long)(&__BL32_END__)
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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/*******************************************************************************
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* Initialize the UART
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******************************************************************************/
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void tsp_early_platform_setup(void)
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{
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/*
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* Initialize a different console than already in use to display
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* messages from TSP
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*/
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console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
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}
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/*******************************************************************************
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* Perform platform specific setup placeholder
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******************************************************************************/
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void tsp_platform_setup(void)
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{
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plat_gic_init();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this only intializes the MMU
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******************************************************************************/
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void tsp_plat_arch_setup(void)
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{
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configure_mmu_el1(BL32_RO_BASE,
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(BL32_END - BL32_RO_BASE),
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BL32_RO_BASE,
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BL32_RO_LIMIT
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#if USE_COHERENT_MEM
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, BL32_COHERENT_RAM_BASE,
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BL32_COHERENT_RAM_LIMIT
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#endif
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);
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}
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