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https://github.com/ARM-software/arm-trusted-firmware.git
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ab8707e687
This patch extends the build option `USE_COHERENT_MEMORY` to conditionally remove coherent memory from the memory maps of all boot loader stages. The patch also adds necessary documentation for coherent memory removal in firmware-design, porting and user guides. Fixes ARM-Software/tf-issues#106 Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
212 lines
6 KiB
C
212 lines
6 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <xlat_tables.h>
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#include "../juno_def.h"
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#define MAP_MHU_SECURE MAP_REGION_FLAT(MHU_SECURE_BASE, \
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MHU_SECURE_SIZE, \
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(MHU_PAYLOAD_CACHED ? \
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MT_MEMORY : MT_DEVICE) \
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| MT_RW | MT_SECURE)
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#define MAP_FLASH MAP_REGION_FLAT(FLASH_BASE, \
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FLASH_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_IOFPGA MAP_REGION_FLAT(IOFPGA_BASE, \
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IOFPGA_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_NS_DRAM MAP_REGION_FLAT(DRAM_NS_BASE, \
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DRAM_NS_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* Table of regions for different BL stages to map using the MMU.
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* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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#if IMAGE_BL1
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static const mmap_region_t juno_mmap[] = {
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MAP_MHU_SECURE,
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MAP_FLASH,
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MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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{0}
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};
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#endif
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#if IMAGE_BL2
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static const mmap_region_t juno_mmap[] = {
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MAP_MHU_SECURE,
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MAP_FLASH,
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MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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MAP_NS_DRAM,
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MAP_TSP_MEM,
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{0}
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};
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#endif
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#if IMAGE_BL31
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static const mmap_region_t juno_mmap[] = {
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MAP_MHU_SECURE,
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MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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{0}
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};
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#endif
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#if IMAGE_BL32
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static const mmap_region_t juno_mmap[] = {
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MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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{0}
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};
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#endif
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/* Array of secure interrupts to be configured by the gic driver */
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const unsigned int irq_sec_array[] = {
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IRQ_MHU,
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IRQ_GPU_SMMU_0,
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IRQ_GPU_SMMU_1,
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IRQ_ETR_SMMU,
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IRQ_TZC400,
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IRQ_TZ_WDOG,
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IRQ_SEC_PHY_TIMER,
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IRQ_SEC_SGI_0,
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IRQ_SEC_SGI_1,
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IRQ_SEC_SGI_2,
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IRQ_SEC_SGI_3,
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IRQ_SEC_SGI_4,
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IRQ_SEC_SGI_5,
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IRQ_SEC_SGI_6,
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IRQ_SEC_SGI_7
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};
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const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
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sizeof(irq_sec_array[0]);
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/*******************************************************************************
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* Macro generating the code for the function setting up the pagetables as per
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* the platform memory map & initialize the mmu, for the given exception level
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******************************************************************************/
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#if USE_COHERENT_MEM
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void configure_mmu_el##_el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long ro_start, \
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unsigned long ro_limit, \
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unsigned long coh_start, \
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unsigned long coh_limit) \
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{ \
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mmap_add_region(total_base, total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(ro_start, ro_start, \
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ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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mmap_add_region(coh_start, coh_start, \
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coh_limit - coh_start, \
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MT_DEVICE | MT_RW | MT_SECURE); \
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mmap_add(juno_mmap); \
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init_xlat_tables(); \
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\
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enable_mmu_el##_el(0); \
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}
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#else
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void configure_mmu_el##_el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long ro_start, \
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unsigned long ro_limit) \
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{ \
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mmap_add_region(total_base, total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(ro_start, ro_start, \
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ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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mmap_add(juno_mmap); \
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init_xlat_tables(); \
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\
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enable_mmu_el##_el(0); \
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}
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#endif
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/* Define EL1 and EL3 variants of the function initialising the MMU */
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DEFINE_CONFIGURE_MMU_EL(1)
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DEFINE_CONFIGURE_MMU_EL(3)
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return NS_IMAGE_OFFSET;
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}
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uint64_t plat_get_syscnt_freq(void)
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{
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uint64_t counter_base_frequency;
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/* Read the frequency from Frequency modes table */
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counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
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/* The first entry of the frequency modes table must not be 0 */
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if (counter_base_frequency == 0)
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panic();
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return counter_base_frequency;
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}
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void plat_gic_init(void)
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{
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arm_gic_init(GICC_BASE, GICD_BASE, 0, irq_sec_array, num_sec_irqs);
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}
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