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Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration

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This commit is contained in:
Manish Pandey 2023-03-15 12:45:26 +01:00 • committed by TrustedFirmware Code Review
commit a4c69581ae
51 changed files with 172 additions and 137 deletions
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33
Makefile
View file

@ -646,6 +646,22 @@ endif
include ${PLAT_MAKEFILE_FULL}
# This internal flag is common option which is set to 1 for scenarios
# when the BL2 is running in EL3 level. This occurs in two scenarios -
# 4 world system running BL2 at EL3 and two world system without BL1 running
# BL2 in EL3
ifeq (${RESET_TO_BL2},1)
BL2_RUNS_AT_EL3 := 1
ifeq (${ENABLE_RME},1)
$(error RESET_TO_BL2=1 and ENABLE_RME=1 configuration is not supported at the moment.)
endif
else ifeq (${ENABLE_RME},1)
BL2_RUNS_AT_EL3 := 1
else
BL2_RUNS_AT_EL3 := 0
endif
$(eval $(call MAKE_PREREQ_DIR,${BUILD_PLAT}))
ifeq (${ARM_ARCH_MAJOR},7)
@ -667,7 +683,7 @@ else
endif
ifeq ($(ENABLE_PIE),1)
ifeq ($(BL2_AT_EL3),1)
ifeq ($(RESET_TO_BL2),1)
ifneq ($(BL2_IN_XIP_MEM),1)
BL2_CPPFLAGS += -fpie
BL2_CFLAGS += -fpie
@ -685,7 +701,7 @@ endif
ifeq (${ARCH},aarch64)
BL1_CPPFLAGS += -DIMAGE_AT_EL3
ifeq ($(BL2_AT_EL3),1)
ifeq ($(RESET_TO_BL2),1)
BL2_CPPFLAGS += -DIMAGE_AT_EL3
else
BL2_CPPFLAGS += -DIMAGE_AT_EL1
@ -762,9 +778,9 @@ ifeq ($(HW_ASSISTED_COHERENCY)-$(USE_COHERENT_MEM),1-1)
$(error USE_COHERENT_MEM cannot be enabled with HW_ASSISTED_COHERENCY)
endif
#For now, BL2_IN_XIP_MEM is only supported when BL2_AT_EL3 is 1.
ifeq ($(BL2_AT_EL3)-$(BL2_IN_XIP_MEM),0-1)
$(error "BL2_IN_XIP_MEM is only supported when BL2_AT_EL3 is enabled")
#For now, BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is 1.
ifeq ($(RESET_TO_BL2)-$(BL2_IN_XIP_MEM),0-1)
$(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled")
endif
# For RAS_EXTENSION, require that EAs are handled in EL3 first
@ -1117,7 +1133,7 @@ $(eval $(call assert_booleans,\
USE_ROMLIB \
USE_TBBR_DEFS \
WARMBOOT_ENABLE_DCACHE_EARLY \
BL2_AT_EL3 \
RESET_TO_BL2 \
BL2_IN_XIP_MEM \
BL2_INV_DCACHE \
USE_SPINLOCK_CAS \
@ -1262,7 +1278,8 @@ $(eval $(call add_defines,\
USE_ROMLIB \
USE_TBBR_DEFS \
WARMBOOT_ENABLE_DCACHE_EARLY \
BL2_AT_EL3 \
RESET_TO_BL2 \
BL2_RUNS_AT_EL3 \
BL2_IN_XIP_MEM \
BL2_INV_DCACHE \
USE_SPINLOCK_CAS \
@ -1369,7 +1386,7 @@ $(eval $(call MAKE_BL,bl1))
endif
ifeq (${NEED_BL2},yes)
ifeq (${BL2_AT_EL3}, 0)
ifeq (${RESET_TO_BL2}, 0)
FIP_BL2_ARGS := tb-fw
endif

2
bl2/bl2.mk
View file

@ -25,7 +25,7 @@ BL2_SOURCES += bl2/${ARCH}/bl2_rme_entrypoint.S \
${GPT_LIB_SRCS}
BL2_DEFAULT_LINKER_SCRIPT_SOURCE := bl2/bl2.ld.S
else ifeq (${BL2_AT_EL3},0)
else ifeq (${RESET_TO_BL2},0)
# Normal operation, no RME, no BL2 at EL3
BL2_SOURCES += bl2/${ARCH}/bl2_entrypoint.S
BL2_DEFAULT_LINKER_SCRIPT_SOURCE := bl2/bl2.ld.S

20
bl2/bl2_main.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,9 +27,9 @@
#define NEXT_IMAGE "BL32"
#endif
#if BL2_AT_EL3
#if RESET_TO_BL2
/*******************************************************************************
* Setup function for BL2 when BL2_AT_EL3=1
* Setup function for BL2 when RESET_TO_BL2=1
******************************************************************************/
void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
@ -48,9 +48,10 @@ void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
assert(is_armv8_3_pauth_present());
#endif /* CTX_INCLUDE_PAUTH_REGS */
}
#else /* BL2_AT_EL3 */
#else /* RESET_TO_BL2 */
/*******************************************************************************
* Setup function for BL2 when BL2_AT_EL3=0
* Setup function for BL2 when RESET_TO_BL2=0
******************************************************************************/
void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
@ -69,7 +70,7 @@ void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
assert(is_armv8_3_pauth_present());
#endif /* CTX_INCLUDE_PAUTH_REGS */
}
#endif /* BL2_AT_EL3 */
#endif /* RESET_TO_BL2 */
/*******************************************************************************
* The only thing to do in BL2 is to load further images and pass control to
@ -107,7 +108,7 @@ void bl2_main(void)
/* Teardown the Measured Boot backend */
bl2_plat_mboot_finish();
#if !BL2_AT_EL3 && !ENABLE_RME
#if !BL2_RUNS_AT_EL3
#ifndef __aarch64__
/*
* For AArch32 state BL1 and BL2 share the MMU setup.
@ -132,7 +133,8 @@ void bl2_main(void)
* be passed to next BL image as an argument.
*/
smc(BL1_SMC_RUN_IMAGE, (unsigned long)next_bl_ep_info, 0, 0, 0, 0, 0, 0);
#else /* if BL2_AT_EL3 || ENABLE_RME */
#else /* if BL2_RUNS_AT_EL3 */
NOTICE("BL2: Booting " NEXT_IMAGE "\n");
print_entry_point_info(next_bl_ep_info);
console_flush();
@ -145,5 +147,5 @@ void bl2_main(void)
#endif /* ENABLE_PAUTH */
bl2_run_next_image(next_bl_ep_info);
#endif /* BL2_AT_EL3 && ENABLE_RME */
#endif /* BL2_RUNS_AT_EL3 */
}

7
docs/design/firmware-design.rst
View file

@ -25,7 +25,6 @@ tables. The details of this library can be found in
:ref:`Translation (XLAT) Tables Library`.
TF-A can be built to support either AArch64 or AArch32 execution state.
.. note::
The descriptions in this chapter are for the Arm TrustZone architecture.
@ -484,8 +483,8 @@ to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
this waste, a special mode enables BL2 to execute at EL3, which allows
a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
when the build flag BL2_AT_EL3 is enabled. The main differences in this
mode are:
when the build flag RESET_TO_BL2 is enabled.
The main differences in this mode are:
#. BL2 includes the reset code and the mailbox mechanism to differentiate
cold boot and warm boot. It runs at EL3 doing the arch
@ -2752,7 +2751,7 @@ kernel at boot time. These can be found in the ``fdts`` directory.
--------------
*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _SMCCC: https://developer.arm.com/docs/den0028/latest

20
docs/getting_started/build-options.rst
View file

@ -52,8 +52,14 @@ Common build options
- ``BL2U``: This is an optional build option which specifies the path to
BL2U image. In this case, the BL2U in TF-A will not be built.
- ``BL2_AT_EL3``: This is an optional build option that enables the use of
BL2 at EL3 execution level.
- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset
vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
entrypoint) or 1 (CPU reset to BL2 entrypoint).
The default value is 0.
- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3.
While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be
true in a 4-world system where RESET_TO_BL2 is 0.
- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the
FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
@ -61,8 +67,8 @@ Common build options
- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
(XIP) memory, like BL1. In these use-cases, it is necessary to initialize
the RW sections in RAM, while leaving the RO sections in place. This option
enable this use-case. For now, this option is only supported when BL2_AT_EL3
is set to '1'.
enable this use-case. For now, this option is only supported
when RESET_TO_BL2 is set to '1'.
- ``BL31``: This is an optional build option which specifies the path to
BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
@ -377,8 +383,8 @@ Common build options
- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
support within generic code in TF-A. This option is currently only supported
in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32
(SP_min) for AARCH32. Default is 0.
in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and
in BL32 (SP_min) for AARCH32. Default is 0.
- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
Measurement Framework(PMF). Default is 0.
@ -1199,7 +1205,7 @@ Firmware update options
--------------
*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
.. _DEN0115: https://developer.arm.com/docs/den0115/latest
.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/

4
docs/plat/arm/corstone1000/index.rst
View file

@ -47,7 +47,7 @@ Build Procedure (TF-A only)
ARCH=aarch64 \
TARGET_PLATFORM=<fpga or fvp> \
ENABLE_PIE=1 \
BL2_AT_EL3=1 \
RESET_TO_BL2=1 \
CREATE_KEYS=1 \
GENERATE_COT=1 \
TRUSTED_BOARD_BOOT=1 \
@ -58,4 +58,4 @@ Build Procedure (TF-A only)
BL33=<path to u-boot binary> \
bl2
*Copyright (c) 2021, Arm Limited. All rights reserved.*
*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*

4
docs/plat/stm32mp1.rst
View file

@ -107,11 +107,11 @@ Memory mapping
Boot sequence
~~~~~~~~~~~~~
ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot)
ROM code -> BL2(compiled with RESET_TO_BL2) -> BL32(SP_min)-> BL33(U-Boot)
or if Op-TEE is used:
ROM code -> BL2 (compiled with BL2_AT_EL3) -> OP-TEE -> BL33 (U-Boot)
ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
Build Instructions

7
include/arch/aarch32/el3_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -374,7 +374,7 @@
* ---------------------------------------------------------------------
*/
.if \_init_c_runtime
#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && RESET_TO_BL2)
/* -----------------------------------------------------------------
* Invalidate the RW memory used by the image. This
* includes the data and NOBITS sections. This is done to
@ -426,7 +426,8 @@
/* Restore r12 */
mov r12, r7
#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
#if defined(IMAGE_BL1) || \
(defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM)
/* -----------------------------------------------------
* Copy data from ROM to RAM.
* -----------------------------------------------------

5
include/arch/aarch64/el2_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -347,7 +347,8 @@
sub x1, x1, x0
bl zeromem
#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && \
RESET_TO_BL2 && BL2_IN_XIP_MEM)
adrp x0, __DATA_RAM_START__
add x0, x0, :lo12:__DATA_RAM_START__
adrp x1, __DATA_ROM_START__

7
include/arch/aarch64/el3_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2023 Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -433,7 +433,7 @@
*/
.if \_init_c_runtime
#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
((BL2_AT_EL3 && BL2_INV_DCACHE) || ENABLE_RME))
((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME))
/* -------------------------------------------------------------
* Invalidate the RW memory used by the BL31 image. This
* includes the data and NOBITS sections. This is done to
@ -495,7 +495,8 @@
bl zeromem
#endif
#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
#if defined(IMAGE_BL1) || \
(defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM)
adrp x0, __DATA_RAM_START__
add x0, x0, :lo12:__DATA_RAM_START__
adrp x1, __DATA_ROM_START__

5
include/lib/cpus/aarch32/cpu_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,7 +9,8 @@
#include <arch.h>
#include <lib/cpus/errata_report.h>
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) \
|| (defined(IMAGE_BL2) && RESET_TO_BL2)
#define IMAGE_AT_EL3
#endif

9
include/plat/arm/common/arm_def.h
View file

@ -554,7 +554,7 @@
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#if BL2_AT_EL3
#if RESET_TO_BL2
#if ENABLE_PIE
/*
* As the BL31 image size appears to be increased when built with the ENABLE_PIE
@ -614,10 +614,11 @@
- PLAT_ARM_MAX_BL31_SIZE)
#define BL31_PROGBITS_LIMIT BL2_BASE
/*
* For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is
* because in the BL2_AT_EL3 configuration, BL2 is always resident.
* For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE.
* This is because in the RESET_TO_BL2 configuration,
* BL2 is always resident.
*/
#if BL2_AT_EL3
#if RESET_TO_BL2
#define BL31_LIMIT BL2_BASE
#else
#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)

6
include/plat/common/platform.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -256,8 +256,8 @@ static inline void bl2_plat_mboot_finish(void)
#endif /* MEASURED_BOOT */
/*******************************************************************************
* Mandatory BL2 at EL3 functions: Must be implemented if BL2_AT_EL3 image is
* supported
* Mandatory BL2 at EL3 functions: Must be implemented
* if RESET_TO_BL2 image is supported
******************************************************************************/
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3);

4
lib/aarch64/misc_helpers.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -164,7 +164,7 @@ func zeromem_dczva
* register value and panic if the MMU is disabled.
*/
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
(BL2_AT_EL3 || ENABLE_RME))
BL2_RUNS_AT_EL3)
mrs tmp1, sctlr_el3
#else
mrs tmp1, sctlr_el1

5
lib/cpus/aarch32/cpu_helpers.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -11,7 +11,8 @@
#include <common/bl_common.h>
#include <lib/el3_runtime/cpu_data.h>
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || \
(defined(IMAGE_BL2) && RESET_TO_BL2)
/*
* The reset handler common to all platforms. After a matching
* cpu_ops structure entry is found, the correponding reset_handler

5
lib/cpus/aarch64/cpu_helpers.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,7 +14,8 @@
#include <lib/el3_runtime/cpu_data.h>
/* Reset fn is needed in BL at reset vector */
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || \
(defined(IMAGE_BL2) && RESET_TO_BL2)
/*
* The reset handler common to all platforms. After a matching
* cpu_ops structure entry is found, the correponding reset_handler

4
lib/cpus/errata_report.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -21,7 +21,7 @@
# define BL_STRING "BL31"
#elif !defined(__aarch64__) && defined(IMAGE_BL32)
# define BL_STRING "BL32"
#elif defined(IMAGE_BL2) && BL2_AT_EL3
#elif defined(IMAGE_BL2) && RESET_TO_BL2
# define BL_STRING "BL2"
#else
# error This image should not be printing errata status

6
make_helpers/defaults.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2016-2022, Arm Limited. All rights reserved.
# Copyright (c) 2016-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -30,13 +30,13 @@ ARM_ARCH_MINOR := 0
BASE_COMMIT := origin/master
# Execute BL2 at EL3
BL2_AT_EL3 := 0
RESET_TO_BL2 := 0
# Only use SP packages if SP layout JSON is defined
BL2_ENABLE_SP_LOAD := 0
# BL2 image is stored in XIP memory, for now, this option is only supported
# when BL2_AT_EL3 is 1.
# when RESET_TO_BL2 is 1.
BL2_IN_XIP_MEM := 0
# Do dcache invalidate upon BL2 entry at EL3

4
make_helpers/tbbr/tbbr_tools.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -83,7 +83,7 @@ $(if ${NON_TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${NON_TRUSTED_WORLD
# Add the BL2 CoT (image cert)
ifeq (${NEED_BL2},yes)
ifeq (${BL2_AT_EL3}, 0)
ifeq (${RESET_TO_BL2}, 0)
ifneq (${COT},cca)
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
endif

4
plat/arm/board/fvp/fvp_bl2_setup.c
View file

@ -45,7 +45,7 @@ struct bl_params *plat_get_next_bl_params(void)
arm_bl_params = arm_get_next_bl_params();
#if !BL2_AT_EL3 && !EL3_PAYLOAD_BASE
#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
const struct dyn_cfg_dtb_info_t *fw_config_info;
uintptr_t fw_config_base = 0UL;
entry_point_info_t *ep_info;
@ -99,7 +99,7 @@ struct bl_params *plat_get_next_bl_params(void)
/* Update BL33's ep info with NS HW config address */
param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr;
#endif /* !BL2_AT_EL3 && !EL3_PAYLOAD_BASE */
#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */
return arm_bl_params;
}

10
plat/arm/board/fvp/fvp_bl31_setup.c
View file

@ -25,7 +25,7 @@ void __init bl31_early_platform_setup2(u_register_t arg0,
/* Initialize the console to provide early debug support */
arm_console_boot_init();
#if !RESET_TO_BL31 && !BL2_AT_EL3
#if !RESET_TO_BL31 && !RESET_TO_BL2
const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
@ -47,7 +47,7 @@ void __init bl31_early_platform_setup2(u_register_t arg0,
assert(hw_config_info != NULL);
assert(hw_config_info->secondary_config_addr != 0UL);
arg2 = hw_config_info->secondary_config_addr;
#endif /* !RESET_TO_BL31 && !BL2_AT_EL3 */
#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 */
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
@ -93,7 +93,7 @@ void __init bl31_plat_arch_setup(void)
* TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support
* gets deprecated.
*/
#if !RESET_TO_BL31 && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1
#if !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1
assert(hw_config_info != NULL);
assert(hw_config_info->config_addr != 0UL);
@ -129,14 +129,14 @@ void __init bl31_plat_arch_setup(void)
rc);
panic();
}
#endif /* !RESET_TO_BL31 && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1 */
#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1 */
}
unsigned int plat_get_syscnt_freq2(void)
{
unsigned int counter_base_frequency;
#if !RESET_TO_BL31 && !BL2_AT_EL3
#if !RESET_TO_BL31 && !RESET_TO_BL2
/* Get the frequency through FCONF API for HW_CONFIG */
counter_base_frequency = FCONF_GET_PROPERTY(hw_config, cpu_timer, clock_freq);
if (counter_base_frequency > 0U) {

4
plat/arm/board/fvp/fvp_common.c
View file

@ -123,13 +123,13 @@ const mmap_region_t plat_arm_mmap[] = {
MAP_DEVICE2,
#endif /* TRUSTED_BOARD_BOOT */
#if CRYPTO_SUPPORT && !BL2_AT_EL3
#if CRYPTO_SUPPORT && !RESET_TO_BL2
/*
* To access shared the Mbed TLS heap while booting the
* system with Crypto support
*/
ARM_MAP_BL1_RW,
#endif /* CRYPTO_SUPPORT && !BL2_AT_EL3 */
#endif /* CRYPTO_SUPPORT && !RESET_TO_BL2 */
#if SPM_MM || SPMC_AT_EL3
ARM_SP_IMAGE_MMAP,
#endif

6
plat/arm/board/fvp/fvp_console.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -24,9 +24,9 @@ void arm_console_runtime_init(void)
/*
* fconf APIs are not supported for RESET_TO_SP_MIN, RESET_TO_BL31 and
* BL2_AT_EL3 systems.
* RESET_TO_BL2 systems.
*/
#if RESET_TO_SP_MIN || RESET_TO_BL31 || BL2_AT_EL3
#if RESET_TO_SP_MIN || RESET_TO_BL31 || RESET_TO_BL2
uart_base = PLAT_ARM_RUN_UART_BASE;
uart_clk = PLAT_ARM_RUN_UART_CLK_IN_HZ;
#else

6
plat/arm/board/fvp/fvp_topology.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -34,9 +34,9 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
/*
* fconf APIs are not supported for RESET_TO_SP_MIN, RESET_TO_BL31 and
* BL2_AT_EL3 systems.
* RESET_TO_BL2 systems.
*/
#if RESET_TO_SP_MIN || RESET_TO_BL31 || BL2_AT_EL3
#if RESET_TO_SP_MIN || RESET_TO_BL31 || RESET_TO_BL2
cluster_count = FVP_CLUSTER_COUNT;
cpus_per_cluster = FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU;
#else

13
plat/arm/board/fvp/platform.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -65,7 +65,8 @@ FVP_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c
ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
ifeq ($(filter 1,${RESET_TO_BL2} \
${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
endif
@ -202,7 +203,7 @@ ifeq (${ENABLE_FEAT_RNG_TRAP},1)
BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c
endif
ifeq (${BL2_AT_EL3},1)
ifeq (${RESET_TO_BL2},1)
BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
plat/arm/board/fvp/fvp_bl2_el3_setup.c \
${FVP_CPU_LIBS} \
@ -238,7 +239,7 @@ BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
# Support for fconf in BL31
# Added separately from the above list for better readability
ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),)
ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
BL31_SOURCES += lib/fconf/fconf.c \
lib/fconf/fconf_dyn_cfg_getter.c \
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
@ -338,7 +339,7 @@ ifeq (${ARCH},aarch32)
endif
# Enable the dynamic translation tables library.
ifeq ($(filter 1,${BL2_AT_EL3} ${ARM_XLAT_TABLES_LIB_V1}),)
ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),)
ifeq (${ARCH},aarch32)
BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
else # AArch64
@ -364,7 +365,7 @@ endif
# Add support for platform supplied linker script for BL31 build
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
ifneq (${BL2_AT_EL3}, 0)
ifneq (${RESET_TO_BL2}, 0)
override BL1_SOURCES =
endif

17
plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,7 +22,7 @@ void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
/* Initialize the console to provide early debug support */
arm_console_boot_init();
#if !RESET_TO_SP_MIN && !BL2_AT_EL3
#if !RESET_TO_SP_MIN && !RESET_TO_BL2
INFO("SP_MIN FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
/* Fill the properties struct with the info from the config dtb */
@ -32,7 +32,7 @@ void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
if (tos_fw_config_info != NULL) {
arg1 = tos_fw_config_info->config_addr;
}
#endif /* !RESET_TO_SP_MIN && !BL2_AT_EL3 */
#endif /* !RESET_TO_SP_MIN && !RESET_TO_BL2 */
arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
@ -68,13 +68,14 @@ void sp_min_plat_arch_setup(void)
* For RESET_TO_SP_MIN systems, SP_MIN(BL32) is the first bootloader
* to run. So there is no BL2 to load the HW_CONFIG dtb into memory
* before control is passed to SP_MIN.
* Also, BL2 skips loading HW_CONFIG dtb for BL2_AT_EL3 builds.
* The code below relies on dynamic mapping capability, which is not
* supported by xlat tables lib V1.
* Also, BL2 skips loading HW_CONFIG dtb for
* RESET_TO_BL2 builds.
* The code below relies on dynamic mapping capability,
* which is not supported by xlat tables lib V1.
* TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support
* gets deprecated.
*/
#if !RESET_TO_SP_MIN && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1
#if !RESET_TO_SP_MIN && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
assert(hw_config_info != NULL);
assert(hw_config_info->config_addr != 0UL);
@ -117,5 +118,5 @@ void sp_min_plat_arch_setup(void)
rc);
panic();
}
#endif /* !RESET_TO_SP_MIN && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1 */
#endif /*!RESET_TO_SP_MIN && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1*/
}

4
plat/arm/board/fvp/sp_min/sp_min-fvp.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -23,7 +23,7 @@ BL32_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
# Support for fconf in SP_MIN(BL32)
# Added separately from the above list for better readability
ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_SP_MIN}),)
ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_SP_MIN}),)
BL32_SOURCES += lib/fconf/fconf.c \
lib/fconf/fconf_dyn_cfg_getter.c \
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c \

4
plat/arm/board/juno/juno_common.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -50,7 +50,7 @@ const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_OPTEE_CORE_MEM,
ARM_OPTEE_PAGEABLE_LOAD_MEM,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
ARM_MAP_BL1_RW,
#endif
{0}

4
plat/arm/board/morello/morello_plat.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -42,7 +42,7 @@ const mmap_region_t plat_arm_mmap[] = {
MORELLO_MAP_NS_SRAM,
ARM_MAP_DRAM1,
ARM_MAP_DRAM2,
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
ARM_MAP_BL1_RW,
#endif
{0}

4
plat/arm/board/n1sdp/n1sdp_plat.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
* Copyright (c) 2018-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -33,7 +33,7 @@ const mmap_region_t plat_arm_mmap[] = {
N1SDP_MAP_NS_SRAM,
ARM_MAP_DRAM1,
ARM_MAP_DRAM2,
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
ARM_MAP_BL1_RW,
#endif
{0}

4
plat/arm/board/tc/tc_plat.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -48,7 +48,7 @@ const mmap_region_t plat_arm_mmap[] = {
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
ARM_MAP_BL1_RW,
#endif
#ifdef SPD_opteed

8
plat/arm/common/arm_bl2_el3_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -34,7 +34,7 @@ void arm_bl2_el3_early_platform_setup(void)
/*
* Allow BL2 to see the whole Trusted RAM. This is determined
* statically since we cannot rely on BL1 passing this information
* in the BL2_AT_EL3 case.
* in the RESET_TO_BL2 case.
*/
bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE;
bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE;
@ -71,7 +71,9 @@ void arm_bl2_el3_plat_arch_setup(void)
{
#if USE_COHERENT_MEM
/* Ensure ARM platforms dont use coherent memory in BL2_AT_EL3 */
/* Ensure ARM platforms dont use coherent memory
* in RESET_TO_BL2
*/
assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U);
#endif

4
plat/arm/common/arm_common.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -283,7 +283,7 @@ DYN_CFG_SOURCES += ${FDT_WRAPPERS_SOURCES}
BL1_SOURCES += ${DYN_CFG_SOURCES}
BL2_SOURCES += ${DYN_CFG_SOURCES}
ifeq (${BL2_AT_EL3},1)
ifeq (${RESET_TO_BL2},1)
BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c
endif

4
plat/arm/common/arm_dyn_cfg.c
View file

@ -45,9 +45,9 @@ int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
assert(heap_addr != NULL);
assert(heap_size != NULL);
#if defined(IMAGE_BL1) || BL2_AT_EL3 || defined(IMAGE_BL31)
#if defined(IMAGE_BL1) || RESET_TO_BL2 || defined(IMAGE_BL31)
/* If in BL1 or BL2_AT_EL3 define a heap */
/* If in BL1 or RESET_TO_BL2 define a heap */
static unsigned char heap[TF_MBEDTLS_HEAP_SIZE];
*heap_addr = heap;

4
plat/arm/css/sgi/sgi_plat.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -64,7 +64,7 @@ const mmap_region_t plat_arm_mmap[] = {
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
ARM_MAP_BL1_RW,
#endif
{0}

4
plat/arm/css/sgi/sgi_plat_v2.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -57,7 +57,7 @@ const mmap_region_t plat_arm_mmap[] = {
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
ARM_MAP_BL1_RW,
#endif
{0}

4
plat/hisilicon/hikey/platform.mk
View file

@ -1,11 +1,11 @@
#
# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Non-TF Boot ROM
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
# or SRAM.

4
plat/hisilicon/hikey960/platform.mk
View file

@ -1,11 +1,11 @@
#
# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Non-TF Boot ROM
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
# On Hikey960, the TSP can execute from TZC secure area in DRAM.
HIKEY960_TSP_RAM_LOCATION ?= dram

4
plat/imx/imx7/picopi/platform.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -22,7 +22,7 @@ WORKAROUND_CVE_2017_5715 := 0
RESET_TO_BL31 := 0
# Non-TF Boot ROM
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
# Indicate single-core
COLD_BOOT_SINGLE_CPU := 1

4
plat/imx/imx7/warp7/platform.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -22,7 +22,7 @@ WORKAROUND_CVE_2017_5715 := 0
RESET_TO_BL31 := 0
# Non-TF Boot ROM
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
# Indicate single-core
COLD_BOOT_SINGLE_CPU := 1

4
plat/imx/imx8m/imx8mm/platform.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -101,7 +101,7 @@ ifeq (${NEED_BL2},yes)
$(eval $(call add_define,NEED_BL2))
LOAD_IMAGE_V2 := 1
# Non-TF Boot ROM
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
endif
ifneq (${TRUSTED_BOARD_BOOT},0)

2
plat/imx/imx8m/imx8mp/platform.mk
View file

@ -98,7 +98,7 @@ ifeq (${NEED_BL2},yes)
$(eval $(call add_define,NEED_BL2))
LOAD_IMAGE_V2 := 1
# Non-TF Boot ROM
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
endif
ifneq (${TRUSTED_BOARD_BOOT},0)

4
plat/intel/soc/agilex/platform.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@ -77,7 +77,7 @@ BL31_SOURCES += \
plat/intel/soc/common/soc/socfpga_reset_manager.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
USE_COHERENT_MEM := 1

2
plat/intel/soc/n5x/platform.mk
View file

@ -46,7 +46,7 @@ BL31_SOURCES += \
plat/intel/soc/common/soc/socfpga_reset_manager.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
USE_COHERENT_MEM := 1

4
plat/intel/soc/stratix10/platform.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@ -76,5 +76,5 @@ BL31_SOURCES += \
plat/intel/soc/common/soc/socfpga_reset_manager.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
USE_COHERENT_MEM := 1

2
plat/nxp/common/setup/common.mk
View file

@ -7,7 +7,7 @@
###############################################################################
# Flow begins in BL2 at EL3 mode
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
# Though one core is powered up by default, there are
# platform specific ways to release more than one core

2
plat/nxp/soc-ls1046a/aarch64/ls1046a_helpers.S
View file

@ -44,7 +44,7 @@ endfunc apply_platform_errata
func plat_reset_handler
mov x29, x30
#if (defined(IMAGE_BL2) && BL2_AT_EL3)
#if (defined(IMAGE_BL2) && RESET_TO_BL2)
bl l2_mem_init
#endif
bl apply_platform_errata

2
plat/renesas/common/common.mk
View file

@ -10,7 +10,7 @@ ARM_CCI_PRODUCT_ID := 500
TRUSTED_BOARD_BOOT := 1
RESET_TO_BL31 := 1
GENERATE_COT := 1
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
ENABLE_SVE_FOR_NS := 0
MULTI_CONSOLE_API := 1

4
plat/socionext/synquacer/platform.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -17,7 +17,7 @@ override TRUSTED_BOARD_BOOT := 0
SQ_USE_SCMI_DRIVER ?= 0
else
override RESET_TO_BL31 := 0
override BL2_AT_EL3 := 1
override RESET_TO_BL2 := 1
SQ_USE_SCMI_DRIVER := 1
BL2_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
endif

4
plat/socionext/uniphier/platform.mk
View file

@ -1,10 +1,10 @@
#
# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
override BL2_AT_EL3 := 1
override RESET_TO_BL2 := 1
override COLD_BOOT_SINGLE_CPU := 1
override PROGRAMMABLE_RESET_ADDRESS := 1
override USE_COHERENT_MEM := 1

2
plat/st/stm32mp1/platform.mk
View file

@ -6,7 +6,7 @@
ARM_CORTEX_A7 := yes
ARM_WITH_NEON := yes
BL2_AT_EL3 := 1
RESET_TO_BL2 := 1
USE_COHERENT_MEM := 0
STM32MP_EARLY_CONSOLE ?= 0