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https://github.com/ARM-software/arm-trusted-firmware.git
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42d4d3baac
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
457 lines
11 KiB
ArmAsm
457 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cpu_macros.S>
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#include <lib/cpus/errata_report.h>
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#include <lib/el3_runtime/cpu_data.h>
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/* Reset fn is needed in BL at reset vector */
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || \
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(defined(IMAGE_BL2) && RESET_TO_BL2)
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/*
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* The reset handler common to all platforms. After a matching
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* cpu_ops structure entry is found, the correponding reset_handler
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* in the cpu_ops is invoked.
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* Clobbers: x0 - x19, x30
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*/
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.globl reset_handler
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func reset_handler
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mov x19, x30
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/* The plat_reset_handler can clobber x0 - x18, x30 */
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bl plat_reset_handler
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops reset handler */
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ldr x2, [x0, #CPU_RESET_FUNC]
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mov x30, x19
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cbz x2, 1f
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/* The cpu_ops reset handler can clobber x0 - x19, x30 */
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br x2
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1:
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ret
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endfunc reset_handler
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#endif
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#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
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/*
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* void prepare_cpu_pwr_dwn(unsigned int power_level)
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*
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* Prepare CPU power down function for all platforms. The function takes
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* a domain level to be powered down as its parameter. After the cpu_ops
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* pointer is retrieved from cpu_data, the handler for requested power
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* level is called.
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*/
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.globl prepare_cpu_pwr_dwn
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func prepare_cpu_pwr_dwn
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/*
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* If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
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* power down handler for the last power level
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*/
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mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1)
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cmp x0, x2
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csel x2, x2, x0, hi
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mrs x1, tpidr_el3
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ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the appropriate power down handler */
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mov x1, #CPU_PWR_DWN_OPS
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add x1, x1, x2, lsl #3
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ldr x1, [x0, x1]
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#if ENABLE_ASSERTIONS
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cmp x1, #0
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ASM_ASSERT(ne)
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#endif
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br x1
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endfunc prepare_cpu_pwr_dwn
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/*
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* Initializes the cpu_ops_ptr if not already initialized
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* in cpu_data. This can be called without a runtime stack, but may
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* only be called after the MMU is enabled.
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* clobbers: x0 - x6, x10
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*/
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.globl init_cpu_ops
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func init_cpu_ops
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mrs x6, tpidr_el3
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ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR]
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cbnz x0, 1f
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mov x10, x30
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bl get_cpu_ops_ptr
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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str x0, [x6, #CPU_DATA_CPU_OPS_PTR]!
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mov x30, x10
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1:
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ret
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endfunc init_cpu_ops
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#endif /* IMAGE_BL31 */
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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/*
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* The cpu specific registers which need to be reported in a crash
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* are reported via cpu_ops cpu_reg_dump function. After a matching
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* cpu_ops structure entry is found, the correponding cpu_reg_dump
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* in the cpu_ops is invoked.
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*/
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.globl do_cpu_reg_dump
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func do_cpu_reg_dump
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mov x16, x30
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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cbz x0, 1f
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/* Get the cpu_ops cpu_reg_dump */
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ldr x2, [x0, #CPU_REG_DUMP]
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cbz x2, 1f
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blr x2
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1:
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mov x30, x16
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ret
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endfunc do_cpu_reg_dump
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#endif
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/*
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* The below function returns the cpu_ops structure matching the
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* midr of the core. It reads the MIDR_EL1 and finds the matching
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* entry in cpu_ops entries. Only the implementation and part number
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* are used to match the entries.
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*
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* If cpu_ops for the MIDR_EL1 cannot be found and
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* SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a
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* default cpu_ops with an MIDR value of 0.
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* (Implementation number 0x0 should be reserved for software use
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* and therefore no clashes should happen with that default value).
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*
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* Return :
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* x0 - The matching cpu_ops pointer on Success
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* x0 - 0 on failure.
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* Clobbers : x0 - x5
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*/
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.globl get_cpu_ops_ptr
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func get_cpu_ops_ptr
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/* Read the MIDR_EL1 */
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mrs x2, midr_el1
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mov_imm x3, CPU_IMPL_PN_MASK
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/* Retain only the implementation and part number using mask */
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and w2, w2, w3
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/* Get the cpu_ops end location */
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adr x5, (__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov x0, #0
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1:
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/* Get the cpu_ops start location */
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adr x4, (__CPU_OPS_START__ + CPU_MIDR)
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2:
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/* Check if we have reached end of list */
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cmp x4, x5
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b.eq search_def_ptr
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/* load the midr from the cpu_ops */
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ldr x1, [x4], #CPU_OPS_SIZE
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and w1, w1, w3
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/* Check if midr matches to midr of this core */
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cmp w1, w2
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b.ne 2b
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/* Subtract the increment and offset to get the cpu-ops pointer */
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sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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#ifdef SUPPORT_UNKNOWN_MPID
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cbnz x2, exit_mpid_found
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/* Mark the unsupported MPID flag */
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adrp x1, unsupported_mpid_flag
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add x1, x1, :lo12:unsupported_mpid_flag
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str w2, [x1]
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exit_mpid_found:
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#endif
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ret
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/*
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* Search again for a default pointer (MIDR = 0x0)
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* or return error if already searched.
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*/
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search_def_ptr:
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#ifdef SUPPORT_UNKNOWN_MPID
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cbz x2, error_exit
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mov x2, #0
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b 1b
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error_exit:
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#endif
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ret
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endfunc get_cpu_ops_ptr
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/*
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* Extract CPU revision and variant, and combine them into a single numeric for
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* easier comparison.
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*/
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.globl cpu_get_rev_var
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func cpu_get_rev_var
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mrs x1, midr_el1
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/*
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* Extract the variant[23:20] and revision[3:0] from MIDR, and pack them
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* as variant[7:4] and revision[3:0] of x0.
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*
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* First extract x1[23:16] to x0[7:0] and zero fill the rest. Then
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* extract x1[3:0] into x0[3:0] retaining other bits.
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*/
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ubfx x0, x1, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS)
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bfxil x0, x1, #MIDR_REV_SHIFT, #MIDR_REV_BITS
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ret
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endfunc cpu_get_rev_var
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/*
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* Compare the CPU's revision-variant (x0) with a given value (x1), for errata
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* application purposes. If the revision-variant is less than or same as a given
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* value, indicates that errata applies; otherwise not.
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*
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* Shall clobber: x0-x3
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*/
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.globl cpu_rev_var_ls
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func cpu_rev_var_ls
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mov x2, #ERRATA_APPLIES
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mov x3, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x0, x2, x3, ls
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ret
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endfunc cpu_rev_var_ls
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/*
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* Compare the CPU's revision-variant (x0) with a given value (x1), for errata
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* application purposes. If the revision-variant is higher than or same as a
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* given value, indicates that errata applies; otherwise not.
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*
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* Shall clobber: x0-x3
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*/
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.globl cpu_rev_var_hs
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func cpu_rev_var_hs
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mov x2, #ERRATA_APPLIES
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mov x3, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x0, x2, x3, hs
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ret
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endfunc cpu_rev_var_hs
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/*
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* Compare the CPU's revision-variant (x0) with a given range (x1 - x2), for errata
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* application purposes. If the revision-variant is between or includes the given
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* values, this indicates that errata applies; otherwise not.
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*
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* Shall clobber: x0-x4
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*/
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.globl cpu_rev_var_range
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func cpu_rev_var_range
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mov x3, #ERRATA_APPLIES
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mov x4, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x1, x3, x4, hs
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cbz x1, 1f
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cmp x0, x2
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csel x1, x3, x4, ls
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1:
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mov x0, x1
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ret
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endfunc cpu_rev_var_range
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#if REPORT_ERRATA
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/*
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* void print_errata_status(void);
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*
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* Function to print errata status for CPUs of its class. Must be called only:
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*
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* - with MMU and data caches are enabled;
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* - after cpu_ops have been initialized in per-CPU data.
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*/
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.globl print_errata_status
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func print_errata_status
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#ifdef IMAGE_BL1
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/*
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* BL1 doesn't have per-CPU data. So retrieve the CPU operations
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* directly.
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*/
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stp xzr, x30, [sp, #-16]!
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bl get_cpu_ops_ptr
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ldp xzr, x30, [sp], #16
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ldr x1, [x0, #CPU_ERRATA_FUNC]
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cbnz x1, .Lprint
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#else
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/*
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* Retrieve pointer to cpu_ops from per-CPU data, and further, the
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* errata printing function. If it's non-NULL, jump to the function in
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* turn.
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*/
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mrs x0, tpidr_el3
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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ldr x1, [x0, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp x1, #0
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ASM_ASSERT(ne)
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#endif
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ldr x0, [x1, #CPU_ERRATA_FUNC]
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cbz x0, .Lnoprint
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/*
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* Printing errata status requires atomically testing the printed flag.
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*/
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stp x19, x30, [sp, #-16]!
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mov x19, x0
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/*
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* Load pointers to errata lock and printed flag. Call
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* errata_needs_reporting to check whether this CPU needs to report
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* errata status pertaining to its class.
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*/
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ldr x0, [x1, #CPU_ERRATA_LOCK]
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ldr x1, [x1, #CPU_ERRATA_PRINTED]
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bl errata_needs_reporting
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mov x1, x19
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ldp x19, x30, [sp], #16
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cbnz x0, .Lprint
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#endif
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.Lnoprint:
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ret
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.Lprint:
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/* Jump to errata reporting function for this CPU */
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br x1
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endfunc print_errata_status
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#endif
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/*
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* int check_wa_cve_2017_5715(void);
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*
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* This function returns:
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* - ERRATA_APPLIES when firmware mitigation is required.
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* - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
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* - ERRATA_MISSING when firmware mitigation would be required but
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* is not compiled in.
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*
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* NOTE: Must be called only after cpu_ops have been initialized
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* in per-CPU data.
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*/
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.globl check_wa_cve_2017_5715
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func check_wa_cve_2017_5715
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mrs x0, tpidr_el3
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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ldr x0, [x0, #CPU_EXTRA1_FUNC]
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/*
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* If the reserved function pointer is NULL, this CPU
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* is unaffected by CVE-2017-5715 so bail out.
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*/
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cmp x0, #CPU_NO_EXTRA1_FUNC
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beq 1f
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br x0
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_wa_cve_2017_5715
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/*
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* void *wa_cve_2018_3639_get_disable_ptr(void);
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*
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* Returns a function pointer which is used to disable mitigation
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* for CVE-2018-3639.
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* The function pointer is only returned on cores that employ
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* dynamic mitigation. If the core uses static mitigation or is
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* unaffected by CVE-2018-3639 this function returns NULL.
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*
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* NOTE: Must be called only after cpu_ops have been initialized
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* in per-CPU data.
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*/
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.globl wa_cve_2018_3639_get_disable_ptr
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func wa_cve_2018_3639_get_disable_ptr
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mrs x0, tpidr_el3
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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ldr x0, [x0, #CPU_EXTRA2_FUNC]
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ret
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endfunc wa_cve_2018_3639_get_disable_ptr
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/*
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* int check_smccc_arch_wa3_applies(void);
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*
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* This function checks whether SMCCC_ARCH_WORKAROUND_3 is enabled to mitigate
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* CVE-2022-23960 for this CPU. It returns:
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* - ERRATA_APPLIES when SMCCC_ARCH_WORKAROUND_3 can be invoked to mitigate
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* the CVE.
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* - ERRATA_NOT_APPLIES when SMCCC_ARCH_WORKAROUND_3 should not be invoked to
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* mitigate the CVE.
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*
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* NOTE: Must be called only after cpu_ops have been initialized
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* in per-CPU data.
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*/
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.globl check_smccc_arch_wa3_applies
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func check_smccc_arch_wa3_applies
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mrs x0, tpidr_el3
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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ldr x0, [x0, #CPU_EXTRA3_FUNC]
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/*
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* If the reserved function pointer is NULL, this CPU
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* is unaffected by CVE-2022-23960 so bail out.
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*/
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cmp x0, #CPU_NO_EXTRA3_FUNC
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beq 1f
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br x0
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_smccc_arch_wa3_applies
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