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42d4d3baac
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
105 lines
2.6 KiB
Makefile
105 lines
2.6 KiB
Makefile
#
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# Copyright 2018-2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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###############################################################################
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# Flow begins in BL2 at EL3 mode
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RESET_TO_BL2 := 1
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# Though one core is powered up by default, there are
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# platform specific ways to release more than one core
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COLD_BOOT_SINGLE_CPU := 0
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PROGRAMMABLE_RESET_ADDRESS := 1
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USE_COHERENT_MEM := 0
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# Use generic OID definition (tbbr_oid.h)
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USE_TBBR_DEFS := 1
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PLAT_XLAT_TABLES_DYNAMIC := 0
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ENABLE_SVE_FOR_NS := 0
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ENABLE_STACK_PROTECTOR := 0
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ERROR_DEPRECATED := 0
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LS_DISABLE_TRUSTED_WDOG := 1
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# On ARM platforms, separate the code and read-only data sections to allow
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# mapping the former as executable and the latter as execute-never.
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SEPARATE_CODE_AND_RODATA := 1
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# Enable new version of image loading on ARM platforms
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LOAD_IMAGE_V2 := 1
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RCW := ""
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ifneq (${SPD},none)
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$(eval $(call add_define, NXP_LOAD_BL32))
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endif
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###############################################################################
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PLAT_TOOL_PATH := tools/nxp
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CREATE_PBL_TOOL_PATH := ${PLAT_TOOL_PATH}/create_pbl
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PLAT_SETUP_PATH := ${PLAT_PATH}/common/setup
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PLAT_INCLUDES += -I${PLAT_SETUP_PATH}/include \
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-Iinclude/plat/arm/common \
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-Iinclude/drivers/arm \
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-Iinclude/lib \
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-Iinclude/drivers/io \
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-Ilib/psci
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# Required without TBBR.
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# To include the defines for DDR PHY Images.
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PLAT_INCLUDES += -Iinclude/common/tbbr
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include ${PLAT_SETUP_PATH}/core.mk
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PLAT_BL_COMMON_SOURCES += ${CPU_LIBS} \
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plat/nxp/common/setup/ls_err.c \
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plat/nxp/common/setup/ls_common.c
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ifneq (${ENABLE_STACK_PROTECTOR},0)
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PLAT_BL_COMMON_SOURCES += ${PLAT_SETUP_PATH}/ls_stack_protector.c
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endif
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
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BL2_SOURCES += drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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drivers/io/io_storage.c \
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common/desc_image_load.c \
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plat/nxp/common/setup/ls_image_load.c \
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plat/nxp/common/setup/ls_io_storage.c \
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plat/nxp/common/setup/ls_bl2_el3_setup.c \
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plat/nxp/common/setup/${ARCH}/ls_bl2_mem_params_desc.c
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BL31_SOURCES += plat/nxp/common/setup/ls_bl31_setup.c \
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ifeq (${LS_EL3_INTERRUPT_HANDLER}, yes)
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$(eval $(call add_define, LS_EL3_INTERRUPT_HANDLER))
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BL31_SOURCES += plat/nxp/common/setup/ls_interrupt_mgmt.c
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endif
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ifeq (${TEST_BL31}, 1)
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BL31_SOURCES += ${TEST_SOURCES}
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endif
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# Verify build config
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# -------------------
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ifneq (${LOAD_IMAGE_V2}, 1)
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$(error Error: Layerscape needs LOAD_IMAGE_V2=1)
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else
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$(eval $(call add_define,LOAD_IMAGE_V2))
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endif
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include $(CREATE_PBL_TOOL_PATH)/create_pbl.mk
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