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https://github.com/ARM-software/arm-trusted-firmware.git
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42d4d3baac
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
172 lines
5.3 KiB
Makefile
172 lines
5.3 KiB
Makefile
#
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# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Non-TF Boot ROM
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RESET_TO_BL2 := 1
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# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
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# or SRAM.
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HIKEY_TSP_RAM_LOCATION ?= dram
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ifeq (${HIKEY_TSP_RAM_LOCATION}, dram)
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HIKEY_TSP_RAM_LOCATION_ID = HIKEY_DRAM_ID
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else ifeq (${HIKEY_TSP_RAM_LOCATION}, sram)
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HIKEY_TSP_RAM_LOCATION_ID = HIKEY_SRAM_ID
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else
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$(error "Currently unsupported HIKEY_TSP_RAM_LOCATION value")
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endif
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CONSOLE_BASE := PL011_UART3_BASE
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CRASH_CONSOLE_BASE := PL011_UART3_BASE
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PLAT_PARTITION_MAX_ENTRIES := 12
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PLAT_PL061_MAX_GPIOS := 160
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COLD_BOOT_SINGLE_CPU := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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ENABLE_SVE_FOR_NS := 0
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# Process flags
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$(eval $(call add_define,HIKEY_TSP_RAM_LOCATION_ID))
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$(eval $(call add_define,CONSOLE_BASE))
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$(eval $(call add_define,CRASH_CONSOLE_BASE))
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$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
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$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
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# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
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# in the FIP if the platform requires.
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ifneq ($(BL32_EXTRA1),)
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$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
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endif
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ifneq ($(BL32_EXTRA2),)
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$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
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endif
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USE_COHERENT_MEM := 1
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PLAT_INCLUDES := -Iplat/hisilicon/hikey/include
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PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
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lib/xlat_tables/aarch64/xlat_tables.c \
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lib/xlat_tables/xlat_tables_common.c \
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plat/hisilicon/hikey/aarch64/hikey_common.c
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BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
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drivers/arm/pl061/pl061_gpio.c \
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drivers/arm/sp804/sp804_delay_timer.c \
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drivers/delay_timer/delay_timer.c \
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drivers/gpio/gpio.c \
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drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/io/io_storage.c \
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drivers/mmc/mmc.c \
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drivers/synopsys/emmc/dw_mmc.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/hisilicon/hikey/aarch64/hikey_helpers.S \
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plat/hisilicon/hikey/hikey_bl1_setup.c \
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plat/hisilicon/hikey/hikey_bl_common.c \
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plat/hisilicon/hikey/hikey_io_storage.c
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BL2_SOURCES += common/desc_image_load.c \
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drivers/arm/pl061/pl061_gpio.c \
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drivers/arm/sp804/sp804_delay_timer.c \
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drivers/delay_timer/delay_timer.c \
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drivers/gpio/gpio.c \
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drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/io/io_storage.c \
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drivers/mmc/mmc.c \
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drivers/partition/gpt.c \
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drivers/partition/partition.c \
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drivers/synopsys/emmc/dw_mmc.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/hisilicon/hikey/aarch64/hikey_helpers.S \
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plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c \
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plat/hisilicon/hikey/hikey_bl2_setup.c \
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plat/hisilicon/hikey/hikey_bl_common.c \
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plat/hisilicon/hikey/hikey_security.c \
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plat/hisilicon/hikey/hikey_ddr.c \
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plat/hisilicon/hikey/hikey_image_load.c \
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plat/hisilicon/hikey/hikey_io_storage.c \
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plat/hisilicon/hikey/hisi_dvfs.c \
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plat/hisilicon/hikey/hisi_mcu.c
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ifeq (${SPD},opteed)
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BL2_SOURCES += lib/optee/optee_utils.c
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endif
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include lib/zlib/zlib.mk
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PLAT_INCLUDES += -Ilib/zlib
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BL2_SOURCES += $(ZLIB_SOURCES)
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HIKEY_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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plat/common/plat_gicv2.c
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BL31_SOURCES += drivers/arm/cci/cci.c \
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drivers/arm/sp804/sp804_delay_timer.c \
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drivers/delay_timer/delay_timer.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/common/plat_psci_common.c \
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plat/hisilicon/hikey/aarch64/hikey_helpers.S \
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plat/hisilicon/hikey/hikey_bl31_setup.c \
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plat/hisilicon/hikey/hikey_pm.c \
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plat/hisilicon/hikey/hikey_topology.c \
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plat/hisilicon/hikey/hisi_ipc.c \
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plat/hisilicon/hikey/hisi_pwrc.c \
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plat/hisilicon/hikey/hisi_pwrc_sram.S \
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${HIKEY_GIC_SOURCES}
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ifeq (${ENABLE_PMF}, 1)
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BL31_SOURCES += plat/hisilicon/hikey/hisi_sip_svc.c \
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lib/pmf/pmf_smc.c
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endif
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ifneq (${TRUSTED_BOARD_BOOT},0)
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include drivers/auth/mbedtls/mbedtls_crypto.mk
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include drivers/auth/mbedtls/mbedtls_x509.mk
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AUTH_SOURCES := drivers/auth/auth_mod.c \
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drivers/auth/crypto_mod.c \
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drivers/auth/img_parser_mod.c \
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drivers/auth/tbbr/tbbr_cot_common.c
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BL1_SOURCES += ${AUTH_SOURCES} \
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plat/common/tbbr/plat_tbbr.c \
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plat/hisilicon/hikey/hikey_tbbr.c \
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plat/hisilicon/hikey/hikey_rotpk.S \
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drivers/auth/tbbr/tbbr_cot_bl1.c
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BL2_SOURCES += ${AUTH_SOURCES} \
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plat/common/tbbr/plat_tbbr.c \
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plat/hisilicon/hikey/hikey_tbbr.c \
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plat/hisilicon/hikey/hikey_rotpk.S \
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drivers/auth/tbbr/tbbr_cot_bl2.c
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ROT_KEY = $(BUILD_PLAT)/rot_key.pem
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ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
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$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
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$(BUILD_PLAT)/bl1/hikey_rotpk.o: $(ROTPK_HASH)
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$(BUILD_PLAT)/bl2/hikey_rotpk.o: $(ROTPK_HASH)
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certificates: $(ROT_KEY)
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$(ROT_KEY): | $(BUILD_PLAT)
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@echo " OPENSSL $@"
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$(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
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$(ROTPK_HASH): $(ROT_KEY)
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@echo " OPENSSL $@"
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$(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
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${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
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endif
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# Enable workarounds for selected Cortex-A53 errata.
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ERRATA_A53_836870 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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WORKAROUND_CVE_2017_5715 := 0
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FIP_ALIGN := 512
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