mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-15 00:54:22 +00:00
Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration
* changes: fix(versal2): pass tl address to bl32 fix(xilinx): runtime console to handle dt failure refactor(xilinx): refactor console to support transfer list chore(xilinx): propagate error code feat(versal2): retrieve DT address from transfer list chore(versal2): move xfer-list file paths fix(versal2): update transfer list as optional
This commit is contained in:
Joanna Farley
TrustedFirmware Code Review
commit
7a6230c18c
11 changed files with 196 additions and 53 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
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* Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -12,4 +12,7 @@
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int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
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entry_point_info_t *bl33);
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void *transfer_list_retrieve_dt_address(void);
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bool populate_data_from_xfer_list(void);
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#endif /* PLAT_XFER_LIST_H */
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72
plat/amd/common/plat_fdt.c
Normal file
72
plat/amd/common/plat_fdt.c
Normal file
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@ -0,0 +1,72 @@
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/*
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* Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <common/fdt_fixup.h>
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#include <common/fdt_wrappers.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <plat_fdt.h>
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#include <plat_xfer_list.h>
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#define FIT_CONFS_PATH "/configurations"
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static bool is_fit_image(void *dtb)
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{
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int64_t confs_noffset = 0;
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bool status = true;
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confs_noffset = fdt_path_offset(dtb, FIT_CONFS_PATH);
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/* confs_noffset is only present on FIT image */
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if (confs_noffset < 0) {
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status = false;
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}
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return status;
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}
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int32_t is_valid_dtb(void *fdt)
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{
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int32_t ret = 0;
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ret = fdt_check_header(fdt);
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if (ret != 0) {
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ERROR("Can't read DT at %p\n", fdt);
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goto error;
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}
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ret = fdt_open_into(fdt, fdt, XILINX_OF_BOARD_DTB_MAX_SIZE);
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if (ret < 0) {
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ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
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goto error;
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}
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if (is_fit_image(fdt)) {
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WARN("FIT image detected, TF-A will not update DTB for DDR address space\n");
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ret = -FDT_ERR_NOTFOUND;
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}
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error:
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return ret;
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}
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/* TODO: Reserve TFA memory in DT through custom TL entry */
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void prepare_dtb(void)
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{
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}
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uintptr_t plat_retrieve_dt_addr(void)
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{
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void *dtb = NULL;
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dtb = transfer_list_retrieve_dt_address();
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if (dtb == NULL) {
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WARN("TL header or DT entry is invalid\n");
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}
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return (uintptr_t)dtb;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
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* Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,26 +7,34 @@
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/transfer_list.h>
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#include <platform_def.h>
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/*
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* FIXME: This address should come from firmware before TF-A runs
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* Having this to make sure the transfer list functionality works
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*/
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#define FW_HANDOFF_BASE U(0x1200000)
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#define FW_HANDOFF_SIZE U(0x600000)
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static struct transfer_list_header *tl_hdr;
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static int32_t tl_ops_holder;
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bool populate_data_from_xfer_list(void)
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{
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bool ret = true;
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tl_hdr = (struct transfer_list_header *)FW_HANDOFF_BASE;
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tl_ops_holder = transfer_list_check_header(tl_hdr);
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if ((tl_ops_holder != TL_OPS_ALL) && (tl_ops_holder != TL_OPS_RO)) {
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ret = false;
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}
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return ret;
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}
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int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
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entry_point_info_t *bl33)
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{
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int32_t ret = tl_ops_holder;
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struct transfer_list_entry *te = NULL;
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struct entry_point_info *ep;
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int32_t ret;
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struct entry_point_info *ep = NULL;
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tl_hdr = (struct transfer_list_header *)FW_HANDOFF_BASE;
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ret = transfer_list_check_header(tl_hdr);
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if ((ret == TL_OPS_ALL) || (ret == TL_OPS_RO)) {
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if ((tl_ops_holder == TL_OPS_ALL) || (tl_ops_holder == TL_OPS_RO)) {
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transfer_list_dump(tl_hdr);
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while ((te = transfer_list_next(tl_hdr, te)) != NULL) {
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ep = transfer_list_entry_data(te);
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@ -37,6 +45,9 @@ int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
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continue;
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case SECURE:
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*bl32 = *ep;
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if (!transfer_list_set_handoff_args(tl_hdr, ep)) {
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ERROR("Invalid transfer list\n");
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}
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continue;
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default:
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ERROR("Unrecognized Image Security State %lu\n",
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@ -46,5 +57,21 @@ int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
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}
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}
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}
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return ret;
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}
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void *transfer_list_retrieve_dt_address(void)
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{
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void *dtb = NULL;
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struct transfer_list_entry *te = NULL;
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if ((tl_ops_holder == TL_OPS_ALL) || (tl_ops_holder == TL_OPS_RO)) {
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te = transfer_list_find(tl_hdr, TL_TAG_FDT);
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if (te != NULL) {
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dtb = transfer_list_entry_data(te);
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}
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}
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return dtb;
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}
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@ -1,7 +1,7 @@
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/*
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* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
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* Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -59,8 +59,10 @@ static inline void bl31_set_default_config(void)
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
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#if defined(SPD_opteed)
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#if (TRANSFER_LIST == 0)
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/* NS dtb addr passed to optee_os */
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bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR;
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#endif
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#endif
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
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@ -81,7 +83,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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(void)arg2;
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(void)arg3;
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uint32_t uart_clock;
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#if (TRANSFER_LIST == 1)
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int32_t rc;
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bool tl_status = false;
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#endif
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board_detection();
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@ -124,6 +129,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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default:
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panic();
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}
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#if (TRANSFER_LIST == 1)
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tl_status = populate_data_from_xfer_list();
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if (tl_status != true) {
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WARN("Invalid transfer list\n");
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}
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#endif
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uart_clock = get_uart_clk();
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@ -152,11 +163,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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#if (TRANSFER_LIST == 1)
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rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info);
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if (rc == TL_OPS_NON || rc == TL_OPS_CUS) {
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NOTICE("BL31: TL not found, using default config\n");
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bl31_set_default_config();
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}
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#else
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bl31_set_default_config();
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#endif
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long rev_var = cpu_get_rev_var();
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@ -1,6 +1,6 @@
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# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
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# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
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# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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@ -86,13 +86,14 @@ else
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endif
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endif
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ifdef XILINX_OF_BOARD_DTB_ADDR
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ifeq (${TRANSFER_LIST},0)
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XILINX_OF_BOARD_DTB_ADDR ?= 0x1000000
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$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
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endif
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iplat/xilinx/common/include/ \
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-Iplat/amd/common/include/ \
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-Iplat/xilinx/common/ipi_mailbox_service/ \
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-I${PLAT_PATH}/include/ \
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-Iplat/xilinx/versal/pm_service/
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@ -128,11 +129,8 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
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drivers/scmi-msg/reset_domain.c \
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${PLAT_PATH}/scmi.c
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BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
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BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
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BL31_SOURCES += ${PLAT_PATH}/plat_psci.c \
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common/fdt_wrappers.c \
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plat/xilinx/common/plat_fdt.c \
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plat/xilinx/common/plat_console.c \
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plat/xilinx/common/plat_startup.c \
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plat/xilinx/common/ipi.c \
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|
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@ -153,7 +151,20 @@ $(eval $(call add_define, CORTEX_A78_AE_H_INC))
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endif
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# Enable Handoff protocol using transfer lists
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TRANSFER_LIST := 1
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TRANSFER_LIST ?= 0
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|
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ifeq (${TRANSFER_LIST},1)
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include lib/transfer_list/transfer_list.mk
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BL31_SOURCES += plat/xilinx/common/plat_xfer_list.c
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BL31_SOURCES += plat/amd/common/plat_fdt.c
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BL31_SOURCES += plat/amd/common/plat_xfer_list.c
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else
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BL31_SOURCES += plat/xilinx/common/plat_fdt.c
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endif
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|
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XLNX_DT_CFG ?= 1
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ifeq (${TRANSFER_LIST},0)
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ifndef XILINX_OF_BOARD_DTB_ADDR
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XLNX_DT_CFG := 0
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endif
|
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endif
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$(eval $(call add_define,XLNX_DT_CFG))
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|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -8,9 +8,7 @@
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#define PLAT_FDT_H
|
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|
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void prepare_dtb(void);
|
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|
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#if defined(XILINX_OF_BOARD_DTB_ADDR)
|
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uintptr_t plat_retrieve_dt_addr(void);
|
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int32_t is_valid_dtb(void *fdt);
|
||||
#endif
|
||||
|
||||
#endif /* PLAT_FDT_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -31,9 +31,7 @@ static console_t runtime_console;
|
|||
static console_holder rt_hd_console;
|
||||
#endif
|
||||
|
||||
#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
|
||||
(!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
|
||||
!IS_TFA_IN_OCM(BL31_BASE)))
|
||||
#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && (XLNX_DT_CFG == 1))
|
||||
static dt_uart_info_t dt_uart_info;
|
||||
#endif
|
||||
|
||||
|
|
@ -78,9 +76,7 @@ static void register_console(const console_holder *consoleh, console_t *console)
|
|||
console_set_scope(console, consoleh->console_scope);
|
||||
}
|
||||
|
||||
#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
|
||||
(!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
|
||||
!IS_TFA_IN_OCM(BL31_BASE)))
|
||||
#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && (XLNX_DT_CFG == 1))
|
||||
/**
|
||||
* get_baudrate() - Get the baudrate form DTB.
|
||||
* @dtb: Address of the Device Tree Blob (DTB).
|
||||
|
|
@ -222,7 +218,7 @@ error:
|
|||
static int fdt_get_uart_info(dt_uart_info_t *info)
|
||||
{
|
||||
int node = 0, ret = 0;
|
||||
void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
|
||||
void *dtb = (void *)plat_retrieve_dt_addr();
|
||||
|
||||
ret = is_valid_dtb(dtb);
|
||||
if (ret < 0) {
|
||||
|
|
@ -259,9 +255,7 @@ void setup_console(void)
|
|||
/* For DT code decoding uncomment console registration below */
|
||||
/* register_console(&boot_hd_console, &boot_console); */
|
||||
|
||||
#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
|
||||
(!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
|
||||
!IS_TFA_IN_OCM(BL31_BASE)))
|
||||
#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && (XLNX_DT_CFG == 1))
|
||||
/* Parse DTB console for UART information */
|
||||
if (fdt_get_uart_info(&dt_uart_info) == 0) {
|
||||
if (CONSOLE_IS(dtb)) {
|
||||
|
|
@ -280,16 +274,16 @@ void setup_console(void)
|
|||
INFO("BL31: Early console setup\n");
|
||||
|
||||
#ifdef CONSOLE_RUNTIME
|
||||
#if (RT_CONSOLE_IS(dtb) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
|
||||
(!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
|
||||
!IS_TFA_IN_OCM(BL31_BASE)))
|
||||
rt_hd_console.base = dt_uart_info.base;
|
||||
rt_hd_console.baud_rate = dt_uart_info.baud_rate;
|
||||
rt_hd_console.console_type = dt_uart_info.console_type;
|
||||
#else
|
||||
rt_hd_console.base = (uintptr_t)RT_UART_BASE;
|
||||
rt_hd_console.baud_rate = (uint32_t)UART_BAUDRATE;
|
||||
rt_hd_console.console_type = RT_UART_TYPE;
|
||||
|
||||
#if (RT_CONSOLE_IS(dtb) && (XLNX_DT_CFG == 1))
|
||||
if (dt_uart_info.base != 0U) {
|
||||
rt_hd_console.base = dt_uart_info.base;
|
||||
rt_hd_console.baud_rate = dt_uart_info.baud_rate;
|
||||
rt_hd_console.console_type = dt_uart_info.console_type;
|
||||
}
|
||||
#endif
|
||||
|
||||
if ((rt_hd_console.console_type == boot_hd_console.console_type) &&
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -37,16 +37,15 @@ int32_t is_valid_dtb(void *fdt)
|
|||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
if (fdt_check_header(fdt) != 0) {
|
||||
ret = fdt_check_header(fdt);
|
||||
if (ret != 0) {
|
||||
ERROR("Can't read DT at %p\n", fdt);
|
||||
ret = -FDT_ERR_NOTFOUND;
|
||||
goto error;
|
||||
}
|
||||
|
||||
ret = fdt_open_into(fdt, fdt, XILINX_OF_BOARD_DTB_MAX_SIZE);
|
||||
if (ret < 0) {
|
||||
ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
|
||||
ret = -FDT_ERR_NOTFOUND;
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
|
@ -105,7 +104,7 @@ void prepare_dtb(void)
|
|||
int map_ret = 0;
|
||||
int ret = 0;
|
||||
|
||||
dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
|
||||
dtb = (void *)plat_retrieve_dt_addr();
|
||||
|
||||
if (!IS_TFA_IN_OCM(BL31_BASE)) {
|
||||
|
||||
|
|
@ -157,3 +156,13 @@ void prepare_dtb(void)
|
|||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
uintptr_t plat_retrieve_dt_addr(void)
|
||||
{
|
||||
void *dtb = NULL;
|
||||
|
||||
#if defined(XILINX_OF_BOARD_DTB_ADDR)
|
||||
dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
|
||||
#endif
|
||||
return (uintptr_t)dtb;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
|
||||
# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
|
|
@ -49,8 +49,12 @@ ifdef VERSAL_PLATFORM
|
|||
endif
|
||||
|
||||
ifdef XILINX_OF_BOARD_DTB_ADDR
|
||||
XLNX_DT_CFG := 1
|
||||
$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
|
||||
else
|
||||
XLNX_DT_CFG := 0
|
||||
endif
|
||||
$(eval $(call add_define,XLNX_DT_CFG))
|
||||
|
||||
PLAT_XLAT_TABLES_DYNAMIC := 0
|
||||
ifeq (${PLAT_XLAT_TABLES_DYNAMIC},1)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
|
||||
# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
|
||||
# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
|
|
@ -68,8 +68,12 @@ endif
|
|||
$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
|
||||
|
||||
ifdef XILINX_OF_BOARD_DTB_ADDR
|
||||
XLNX_DT_CFG := 1
|
||||
$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
|
||||
else
|
||||
XLNX_DT_CFG := 0
|
||||
endif
|
||||
$(eval $(call add_define,XLNX_DT_CFG))
|
||||
|
||||
# Runtime console in default console in DEBUG build
|
||||
ifeq ($(DEBUG), 1)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -173,4 +173,10 @@
|
|||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
|
||||
#define XLNX_DT_CFG 1
|
||||
#else
|
||||
#define XLNX_DT_CFG 0
|
||||
#endif
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue