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https://github.com/ARM-software/arm-trusted-firmware.git
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4c5cf47f98
Refactor console to support DTB console in case of transfer list. Simplify logic where SOC specific macros are moved to platform headers or makefile where XLNX_DT_CFG macro describe if system is DT driven or not. Change-Id: Id45c03a950b62e83e91a50e0485eacdb233ba745 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
146 lines
4.4 KiB
Makefile
146 lines
4.4 KiB
Makefile
# Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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override PROGRAMMABLE_RESET_ADDRESS := 1
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PSCI_EXTENDED_STATE_ID := 1
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A53_DISABLE_NON_TEMPORAL_HINT := 0
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SEPARATE_CODE_AND_RODATA := 1
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override RESET_TO_BL31 := 1
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PL011_GENERIC_UART := 1
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IPI_CRC_CHECK := 0
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HARDEN_SLS_ALL := 0
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CPU_PWRDWN_SGI ?= 6
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$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI}))
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# A72 Erratum for SoC
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ERRATA_A72_859971 := 1
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ERRATA_A72_1319367 := 1
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ifdef VERSAL_ATF_MEM_BASE
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$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
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ifndef VERSAL_ATF_MEM_SIZE
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$(error "VERSAL_ATF_MEM_BASE defined without VERSAL_ATF_MEM_SIZE")
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endif
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$(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
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ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
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$(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
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endif
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endif
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ifdef VERSAL_BL32_MEM_BASE
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$(eval $(call add_define,VERSAL_BL32_MEM_BASE))
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ifndef VERSAL_BL32_MEM_SIZE
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$(error "VERSAL_BL32_MEM_BASE defined without VERSAL_BL32_MEM_SIZE")
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endif
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$(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
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endif
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ifdef IPI_CRC_CHECK
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$(eval $(call add_define,IPI_CRC_CHECK))
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endif
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ifdef VERSAL_PLATFORM
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$(warning "VERSAL_PLATFORM has been deprecated")
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endif
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ifdef XILINX_OF_BOARD_DTB_ADDR
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XLNX_DT_CFG := 1
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$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
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else
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XLNX_DT_CFG := 0
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endif
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$(eval $(call add_define,XLNX_DT_CFG))
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PLAT_XLAT_TABLES_DYNAMIC := 0
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ifeq (${PLAT_XLAT_TABLES_DYNAMIC},1)
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$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
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endif
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# enable assert() for release/debug builds
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ENABLE_ASSERTIONS := 1
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iplat/xilinx/common/include/ \
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-Iplat/xilinx/common/ipi_mailbox_service/ \
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-Iplat/xilinx/versal/include/ \
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-Iplat/xilinx/versal/pm_service/
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include lib/libfdt/libfdt.mk
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_BL_COMMON_SOURCES := drivers/arm/dcc/dcc_console.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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${GICV3_SOURCES} \
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drivers/arm/pl011/aarch64/pl011_console.S \
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plat/common/aarch64/crash_console_helpers.S \
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plat/arm/common/arm_cci.c \
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plat/arm/common/arm_common.c \
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plat/common/plat_gicv3.c \
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plat/xilinx/versal/aarch64/versal_helpers.S \
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plat/xilinx/versal/aarch64/versal_common.c \
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${XLAT_TABLES_LIB_SRCS}
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VERSAL_CONSOLE ?= pl011
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ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none))
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else
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$(error "Please define VERSAL_CONSOLE")
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endif
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$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
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# Runtime console in default console in DEBUG build
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ifeq ($(DEBUG), 1)
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CONSOLE_RUNTIME ?= pl011
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endif
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# Runtime console
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ifdef CONSOLE_RUNTIME
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ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb))
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$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
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else
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$(error "Please define CONSOLE_RUNTIME")
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endif
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endif
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BL31_SOURCES += drivers/arm/cci/cci.c \
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lib/cpus/aarch64/cortex_a72.S \
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common/fdt_wrappers.c \
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plat/common/plat_psci_common.c \
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plat/xilinx/common/ipi.c \
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plat/xilinx/common/plat_fdt.c \
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plat/xilinx/common/plat_console.c \
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plat/xilinx/common/plat_clkfunc.c \
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plat/xilinx/common/plat_startup.c \
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plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
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plat/xilinx/common/pm_service/pm_ipi.c \
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plat/xilinx/common/pm_service/pm_api_sys.c \
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plat/xilinx/common/pm_service/pm_svc_main.c \
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plat/xilinx/common/versal.c \
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plat/xilinx/versal/bl31_versal_setup.c \
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plat/xilinx/versal/plat_psci.c \
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plat/xilinx/versal/plat_versal.c \
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plat/xilinx/versal/plat_topology.c \
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plat/xilinx/versal/sip_svc_setup.c \
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plat/xilinx/versal/versal_gicv3.c \
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plat/xilinx/versal/versal_ipi.c \
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plat/xilinx/versal/pm_service/pm_client.c \
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common/fdt_fixup.c \
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${LIBFDT_SRCS}
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ifeq ($(HARDEN_SLS_ALL), 1)
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TF_CFLAGS_aarch64 += -mharden-sls=all
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endif
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ifeq (${ERRATA_ABI_SUPPORT}, 1)
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# enable the cpu macros for errata abi interface
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CORTEX_A72_H_INC := 1
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$(eval $(call add_define, CORTEX_A72_H_INC))
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endif
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