diff --git a/plat/xilinx/common/include/plat_xfer_list.h b/plat/amd/common/include/plat_xfer_list.h
similarity index 64%
rename from plat/xilinx/common/include/plat_xfer_list.h
rename to plat/amd/common/include/plat_xfer_list.h
index cc79a2c68..24a9c0c51 100644
--- a/plat/xilinx/common/include/plat_xfer_list.h
+++ b/plat/amd/common/include/plat_xfer_list.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,4 +12,7 @@
 int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
 				       entry_point_info_t *bl33);
 
+void *transfer_list_retrieve_dt_address(void);
+bool populate_data_from_xfer_list(void);
+
 #endif /* PLAT_XFER_LIST_H */
diff --git a/plat/amd/common/plat_fdt.c b/plat/amd/common/plat_fdt.c
new file mode 100644
index 000000000..e72c0dd22
--- /dev/null
+++ b/plat/amd/common/plat_fdt.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
+#include <libfdt.h>
+#include <platform_def.h>
+
+#include <plat_fdt.h>
+#include <plat_xfer_list.h>
+
+#define FIT_CONFS_PATH	"/configurations"
+
+static bool is_fit_image(void *dtb)
+{
+	int64_t confs_noffset = 0;
+	bool status = true;
+
+	confs_noffset = fdt_path_offset(dtb, FIT_CONFS_PATH);
+
+	/* confs_noffset is only present on FIT image */
+	if (confs_noffset < 0) {
+		status = false;
+	}
+
+	return status;
+}
+
+int32_t is_valid_dtb(void *fdt)
+{
+	int32_t ret = 0;
+
+	ret = fdt_check_header(fdt);
+	if (ret != 0) {
+		ERROR("Can't read DT at %p\n", fdt);
+		goto error;
+	}
+
+	ret = fdt_open_into(fdt, fdt, XILINX_OF_BOARD_DTB_MAX_SIZE);
+	if (ret < 0) {
+		ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
+		goto error;
+	}
+
+	if (is_fit_image(fdt)) {
+		WARN("FIT image detected, TF-A will not update DTB for DDR address space\n");
+		ret = -FDT_ERR_NOTFOUND;
+	}
+error:
+	return ret;
+}
+
+/* TODO: Reserve TFA memory in DT through custom TL entry */
+void prepare_dtb(void)
+{
+
+}
+
+uintptr_t plat_retrieve_dt_addr(void)
+{
+	void *dtb = NULL;
+
+	dtb = transfer_list_retrieve_dt_address();
+	if (dtb == NULL) {
+		WARN("TL header or DT entry is invalid\n");
+	}
+
+	return (uintptr_t)dtb;
+}
diff --git a/plat/xilinx/common/plat_xfer_list.c b/plat/amd/common/plat_xfer_list.c
similarity index 50%
rename from plat/xilinx/common/plat_xfer_list.c
rename to plat/amd/common/plat_xfer_list.c
index eae7ce4e7..7af672688 100644
--- a/plat/xilinx/common/plat_xfer_list.c
+++ b/plat/amd/common/plat_xfer_list.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,26 +7,34 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <lib/transfer_list.h>
+#include <platform_def.h>
 
-/*
- * FIXME: This address should come from firmware before TF-A runs
- * Having this to make sure the transfer list functionality works
- */
-#define FW_HANDOFF_BASE		U(0x1200000)
-#define FW_HANDOFF_SIZE		U(0x600000)
 
 static struct transfer_list_header *tl_hdr;
+static int32_t tl_ops_holder;
+
+bool populate_data_from_xfer_list(void)
+{
+	bool ret = true;
+
+	tl_hdr = (struct transfer_list_header *)FW_HANDOFF_BASE;
+	tl_ops_holder = transfer_list_check_header(tl_hdr);
+
+	if ((tl_ops_holder != TL_OPS_ALL) && (tl_ops_holder != TL_OPS_RO)) {
+		ret = false;
+	}
+
+	return ret;
+}
 
 int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
 				       entry_point_info_t *bl33)
 {
+	int32_t ret = tl_ops_holder;
 	struct transfer_list_entry *te = NULL;
-	struct entry_point_info *ep;
-	int32_t ret;
+	struct entry_point_info *ep = NULL;
 
-	tl_hdr = (struct transfer_list_header *)FW_HANDOFF_BASE;
-	ret = transfer_list_check_header(tl_hdr);
-	if ((ret == TL_OPS_ALL) || (ret == TL_OPS_RO)) {
+	if ((tl_ops_holder == TL_OPS_ALL) || (tl_ops_holder == TL_OPS_RO)) {
 		transfer_list_dump(tl_hdr);
 		while ((te = transfer_list_next(tl_hdr, te)) != NULL) {
 			ep = transfer_list_entry_data(te);
@@ -37,6 +45,9 @@ int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
 					continue;
 				case SECURE:
 					*bl32 = *ep;
+					if (!transfer_list_set_handoff_args(tl_hdr, ep)) {
+						ERROR("Invalid transfer list\n");
+					}
 					continue;
 				default:
 					ERROR("Unrecognized Image Security State %lu\n",
@@ -46,5 +57,21 @@ int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
 			}
 		}
 	}
+
 	return ret;
 }
+
+void *transfer_list_retrieve_dt_address(void)
+{
+	void *dtb = NULL;
+	struct transfer_list_entry *te = NULL;
+
+	if ((tl_ops_holder == TL_OPS_ALL) || (tl_ops_holder == TL_OPS_RO)) {
+		te = transfer_list_find(tl_hdr, TL_TAG_FDT);
+		if (te != NULL) {
+			dtb = transfer_list_entry_data(te);
+		}
+	}
+
+	return dtb;
+}
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 1914830f9..3a856cb05 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -59,8 +59,10 @@ static inline void bl31_set_default_config(void)
 	bl32_image_ep_info.pc = BL32_BASE;
 	bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
 #if defined(SPD_opteed)
+#if (TRANSFER_LIST == 0)
 	/* NS dtb addr passed to optee_os */
 	bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR;
+#endif
 #endif
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 	bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
@@ -81,7 +83,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	(void)arg2;
 	(void)arg3;
 	uint32_t uart_clock;
+#if (TRANSFER_LIST == 1)
 	int32_t rc;
+	bool tl_status = false;
+#endif
 
 	board_detection();
 
@@ -124,6 +129,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	default:
 		panic();
 	}
+#if (TRANSFER_LIST == 1)
+	tl_status = populate_data_from_xfer_list();
+	if (tl_status != true) {
+		WARN("Invalid transfer list\n");
+	}
+#endif
 
 	uart_clock = get_uart_clk();
 
@@ -152,11 +163,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 
+#if (TRANSFER_LIST == 1)
 	rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info);
 	if (rc == TL_OPS_NON || rc == TL_OPS_CUS) {
 		NOTICE("BL31: TL not found, using default config\n");
 		bl31_set_default_config();
 	}
+#else
+	bl31_set_default_config();
+#endif
 
 	long rev_var = cpu_get_rev_var();
 
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 3114976b6..4aedd8a2e 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -1,6 +1,6 @@
 # Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
 # Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
-# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
@@ -86,13 +86,14 @@ else
 endif
 endif
 
-
-ifdef XILINX_OF_BOARD_DTB_ADDR
+ifeq (${TRANSFER_LIST},0)
+XILINX_OF_BOARD_DTB_ADDR ?= 0x1000000
 $(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
 endif
 
 PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
 				-Iplat/xilinx/common/include/			\
+				-Iplat/amd/common/include/			\
 				-Iplat/xilinx/common/ipi_mailbox_service/	\
 				-I${PLAT_PATH}/include/				\
 				-Iplat/xilinx/versal/pm_service/
@@ -128,11 +129,8 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				drivers/scmi-msg/reset_domain.c			\
 				${PLAT_PATH}/scmi.c
 
-BL31_SOURCES		+=	${PLAT_PATH}/plat_psci.c
-
-BL31_SOURCES		+=	plat/xilinx/common/plat_fdt.c			\
+BL31_SOURCES		+=	${PLAT_PATH}/plat_psci.c			\
 				common/fdt_wrappers.c                           \
-				plat/xilinx/common/plat_fdt.c                   \
 				plat/xilinx/common/plat_console.c               \
 				plat/xilinx/common/plat_startup.c		\
 				plat/xilinx/common/ipi.c			\
@@ -153,7 +151,20 @@ $(eval $(call add_define, CORTEX_A78_AE_H_INC))
 endif
 
 # Enable Handoff protocol using transfer lists
-TRANSFER_LIST                   := 1
+TRANSFER_LIST                   ?= 0
 
+ifeq (${TRANSFER_LIST},1)
 include lib/transfer_list/transfer_list.mk
-BL31_SOURCES           +=      plat/xilinx/common/plat_xfer_list.c
+BL31_SOURCES           +=	plat/amd/common/plat_fdt.c
+BL31_SOURCES           +=	plat/amd/common/plat_xfer_list.c
+else
+BL31_SOURCES           +=	plat/xilinx/common/plat_fdt.c
+endif
+
+XLNX_DT_CFG	?= 1
+ifeq (${TRANSFER_LIST},0)
+ifndef XILINX_OF_BOARD_DTB_ADDR
+XLNX_DT_CFG	:= 0
+endif
+endif
+$(eval $(call add_define,XLNX_DT_CFG))
diff --git a/plat/xilinx/common/include/plat_fdt.h b/plat/xilinx/common/include/plat_fdt.h
index 47a678c75..48ffff3c6 100644
--- a/plat/xilinx/common/include/plat_fdt.h
+++ b/plat/xilinx/common/include/plat_fdt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -8,9 +8,7 @@
 #define PLAT_FDT_H
 
 void prepare_dtb(void);
-
-#if defined(XILINX_OF_BOARD_DTB_ADDR)
+uintptr_t plat_retrieve_dt_addr(void);
 int32_t is_valid_dtb(void *fdt);
-#endif
 
 #endif /* PLAT_FDT_H */
diff --git a/plat/xilinx/common/plat_console.c b/plat/xilinx/common/plat_console.c
index 681226f99..617a34550 100644
--- a/plat/xilinx/common/plat_console.c
+++ b/plat/xilinx/common/plat_console.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,9 +31,7 @@ static console_t runtime_console;
 static console_holder rt_hd_console;
 #endif
 
-#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
-	(!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
-				   !IS_TFA_IN_OCM(BL31_BASE)))
+#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && (XLNX_DT_CFG == 1))
 static dt_uart_info_t dt_uart_info;
 #endif
 
@@ -78,9 +76,7 @@ static void register_console(const console_holder *consoleh, console_t *console)
 	console_set_scope(console, consoleh->console_scope);
 }
 
-#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
-	(!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
-				   !IS_TFA_IN_OCM(BL31_BASE)))
+#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && (XLNX_DT_CFG == 1))
 /**
  * get_baudrate() - Get the baudrate form DTB.
  * @dtb: Address of the Device Tree Blob (DTB).
@@ -222,7 +218,7 @@ error:
 static int fdt_get_uart_info(dt_uart_info_t *info)
 {
 	int node = 0, ret = 0;
-	void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
+	void *dtb = (void *)plat_retrieve_dt_addr();
 
 	ret = is_valid_dtb(dtb);
 	if (ret < 0) {
@@ -259,9 +255,7 @@ void setup_console(void)
 	/* For DT code decoding uncomment console registration below */
 	/* register_console(&boot_hd_console, &boot_console); */
 
-#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
-	(!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
-				   !IS_TFA_IN_OCM(BL31_BASE)))
+#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && (XLNX_DT_CFG == 1))
 	/* Parse DTB console for UART information  */
 	if (fdt_get_uart_info(&dt_uart_info) == 0) {
 		if (CONSOLE_IS(dtb)) {
@@ -280,16 +274,16 @@ void setup_console(void)
 	INFO("BL31: Early console setup\n");
 
 #ifdef CONSOLE_RUNTIME
-#if (RT_CONSOLE_IS(dtb) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
-	       (!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
-					!IS_TFA_IN_OCM(BL31_BASE)))
-	rt_hd_console.base = dt_uart_info.base;
-	rt_hd_console.baud_rate = dt_uart_info.baud_rate;
-	rt_hd_console.console_type = dt_uart_info.console_type;
-#else
 	rt_hd_console.base = (uintptr_t)RT_UART_BASE;
 	rt_hd_console.baud_rate = (uint32_t)UART_BAUDRATE;
 	rt_hd_console.console_type = RT_UART_TYPE;
+
+#if (RT_CONSOLE_IS(dtb) && (XLNX_DT_CFG == 1))
+	if (dt_uart_info.base != 0U) {
+		rt_hd_console.base = dt_uart_info.base;
+		rt_hd_console.baud_rate = dt_uart_info.baud_rate;
+		rt_hd_console.console_type = dt_uart_info.console_type;
+	}
 #endif
 
 	if ((rt_hd_console.console_type == boot_hd_console.console_type) &&
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index 4ad7b2d01..62b46a92f 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -37,16 +37,15 @@ int32_t is_valid_dtb(void *fdt)
 {
 	int32_t ret = 0;
 
-	if (fdt_check_header(fdt) != 0) {
+	ret = fdt_check_header(fdt);
+	if (ret != 0) {
 		ERROR("Can't read DT at %p\n", fdt);
-		ret = -FDT_ERR_NOTFOUND;
 		goto error;
 	}
 
 	ret = fdt_open_into(fdt, fdt, XILINX_OF_BOARD_DTB_MAX_SIZE);
 	if (ret < 0) {
 		ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
-		ret = -FDT_ERR_NOTFOUND;
 		goto error;
 	}
 
@@ -105,7 +104,7 @@ void prepare_dtb(void)
 	int map_ret = 0;
 	int ret = 0;
 
-	dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
+	dtb = (void *)plat_retrieve_dt_addr();
 
 	if (!IS_TFA_IN_OCM(BL31_BASE)) {
 
@@ -157,3 +156,13 @@ void prepare_dtb(void)
 	}
 #endif
 }
+
+uintptr_t plat_retrieve_dt_addr(void)
+{
+	void *dtb = NULL;
+
+#if defined(XILINX_OF_BOARD_DTB_ADDR)
+	dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
+#endif
+	return (uintptr_t)dtb;
+}
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 7c15be02f..8be4be6a7 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -1,5 +1,5 @@
 # Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
-# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
@@ -49,8 +49,12 @@ ifdef VERSAL_PLATFORM
 endif
 
 ifdef XILINX_OF_BOARD_DTB_ADDR
+XLNX_DT_CFG     := 1
 $(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
+else
+XLNX_DT_CFG     := 0
 endif
+$(eval $(call add_define,XLNX_DT_CFG))
 
 PLAT_XLAT_TABLES_DYNAMIC := 0
 ifeq (${PLAT_XLAT_TABLES_DYNAMIC},1)
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index 9534118be..25caab47b 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -1,6 +1,6 @@
 # Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
 # Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
-# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
@@ -68,8 +68,12 @@ endif
 $(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
 
 ifdef XILINX_OF_BOARD_DTB_ADDR
+XLNX_DT_CFG     := 1
 $(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
+else
+XLNX_DT_CFG     := 0
 endif
+$(eval $(call add_define,XLNX_DT_CFG))
 
 # Runtime console in default console in DEBUG build
 ifeq ($(DEBUG), 1)
diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index 0c83a568f..9a9c8d1ca 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -173,4 +173,10 @@
 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI,	grp, \
 			GIC_INTR_CFG_EDGE)
 
+#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
+#define XLNX_DT_CFG 1
+#else
+#define XLNX_DT_CFG 0
+#endif
+
 #endif /* PLATFORM_DEF_H */