mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
Merge changes from topic "intel-plat-refactor" into integration
* changes: intel: Platform common code refactor intel: Platform common code refactor
This commit is contained in:
Sandrine Bailleux
TrustedFirmware Code Review
commit
5119fa7b8d
29 changed files with 34 additions and 496 deletions
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@ -15,7 +15,7 @@
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#define PLAT_CPUID_RELEASE 0xffe1b000
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#define PLAT_AGX_SEC_ENTRY 0xffe1b008
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#define PLAT_SEC_ENTRY 0xffe1b008
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/* Define next boot image name and offset */
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#define PLAT_NS_IMAGE_OFFSET 0x50000
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@ -7,7 +7,8 @@
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#
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PLAT_INCLUDES := \
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-Iplat/intel/soc/agilex/include/ \
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-Iplat/intel/soc/common/drivers/
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-Iplat/intel/soc/common/drivers/ \
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-Iplat/intel/soc/common/include/
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PLAT_BL_COMMON_SOURCES := \
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drivers/arm/gic/common/gic_common.c \
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@ -19,8 +20,8 @@ PLAT_BL_COMMON_SOURCES := \
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lib/xlat_tables/aarch64/xlat_tables.c \
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lib/xlat_tables/xlat_tables_common.c \
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plat/common/plat_gicv2.c \
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plat/intel/soc/agilex/aarch64/platform_common.c \
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plat/intel/soc/agilex/aarch64/plat_helpers.S \
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plat/intel/soc/common/aarch64/platform_common.c \
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plat/intel/soc/common/aarch64/plat_helpers.S
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BL2_SOURCES += \
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common/desc_image_load.c \
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@ -37,14 +38,14 @@ BL2_SOURCES += \
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lib/cpus/aarch64/cortex_a53.S \
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plat/intel/soc/agilex/bl2_plat_setup.c \
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plat/intel/soc/agilex/socfpga_storage.c \
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plat/intel/soc/agilex/bl2_plat_mem_params_desc.c \
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plat/intel/soc/common/bl2_plat_mem_params_desc.c \
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plat/intel/soc/agilex/soc/agilex_reset_manager.c \
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plat/intel/soc/agilex/soc/agilex_handoff.c \
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plat/intel/soc/agilex/soc/agilex_clock_manager.c \
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plat/intel/soc/agilex/soc/agilex_pinmux.c \
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plat/intel/soc/agilex/soc/agilex_memory_controller.c \
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plat/intel/soc/agilex/socfpga_delay_timer.c \
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plat/intel/soc/agilex/socfpga_image_load.c \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/common/socfpga_image_load.c \
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plat/intel/soc/agilex/soc/agilex_system_manager.c \
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plat/intel/soc/agilex/soc/agilex_mailbox.c \
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plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
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@ -59,8 +60,8 @@ BL31_SOURCES += \
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plat/intel/soc/agilex/socfpga_sip_svc.c \
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plat/intel/soc/agilex/bl31_plat_setup.c \
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plat/intel/soc/agilex/socfpga_psci.c \
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plat/intel/soc/agilex/socfpga_topology.c \
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plat/intel/soc/agilex/socfpga_delay_timer.c \
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plat/intel/soc/common/socfpga_topology.c \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/agilex/soc/agilex_reset_manager.c \
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plat/intel/soc/agilex/soc/agilex_pinmux.c \
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plat/intel/soc/agilex/soc/agilex_clock_manager.c \
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@ -17,7 +17,7 @@
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#define AGX_RSTMGR_OFST 0xffd11000
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#define AGX_RSTMGR_MPUMODRST_OFST 0x20
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uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_AGX_SEC_ENTRY;
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uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
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uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
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/*******************************************************************************
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@ -34,7 +34,7 @@ func plat_secondary_cold_boot_setup
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poll_mailbox:
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wfi
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mov_imm x0, PLAT_AGX_SEC_ENTRY
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mov_imm x0, PLAT_SEC_ENTRY
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ldr x1, [x0]
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mov_imm x2, PLAT_CPUID_RELEASE
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ldr x3, [x2]
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@ -66,7 +66,7 @@ func plat_my_core_pos
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endfunc plat_my_core_pos
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func plat_get_my_entrypoint
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mov_imm x1, PLAT_AGX_SEC_ENTRY
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mov_imm x1, PLAT_SEC_ENTRY
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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@ -9,8 +9,8 @@
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#define AGX_GLOBAL_TIMER 0xffd01000
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#define AGX_GLOBAL_TIMER_EN 0x3
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#define SOCFPGA_GLOBAL_TIMER 0xffd01000
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#define SOCFPGA_GLOBAL_TIMER_EN 0x3
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/********************************************************************
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* The timer delay function
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@ -35,5 +35,5 @@ static const timer_ops_t plat_timer_ops = {
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void socfpga_delay_timer_init(void)
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{
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timer_init(&plat_timer_ops);
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mmio_write_32(AGX_GLOBAL_TIMER, AGX_GLOBAL_TIMER_EN);
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mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
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}
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@ -1,121 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl platform_is_primary_cpu
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl plat_get_my_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* Wait until the it gets reset signal from rstmgr gets populated */
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poll_mailbox:
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wfi
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mov_imm x0, PLAT_S10_SEC_ENTRY
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ldr x1, [x0]
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mov_imm x2, PLAT_CPUID_RELEASE
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ldr x3, [x2]
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mrs x4, mpidr_el1
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and x4, x4, #0xff
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cmp x3, x4
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b.ne poll_mailbox
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br x1
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endfunc plat_secondary_cold_boot_setup
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func platform_is_primary_cpu
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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b platform_is_primary_cpu
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endfunc plat_is_my_cpu_primary
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_my_core_pos
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func plat_get_my_entrypoint
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mov_imm x1, PLAT_S10_SEC_ENTRY
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, PLAT_UART0_BASE
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mov_imm x1, PLAT_UART_CLOCK
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mov_imm x2, PLAT_BAUDRATE
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b console_16550_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_UART0_BASE
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b console_16550_core_putc
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov_imm x0, CRASH_CONSOLE_BASE
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b console_16550_core_flush
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endfunc plat_crash_console_flush
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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.data
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.align 3
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@ -1,57 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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unsigned int plat_get_syscnt_freq2(void)
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{
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return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return PLAT_NS_IMAGE_OFFSET;
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}
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/******************************************************************************
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* Gets SPSR for BL32 entry
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*****************************************************************************/
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uint32_t plat_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/******************************************************************************
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* Gets SPSR for BL33 entry
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*****************************************************************************/
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uint32_t plat_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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@ -1,96 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <platform_def.h>
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#include <plat/common/platform.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#ifdef SCP_BL2_BASE
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/* Fill SCP_BL2 related information if it exists */
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{
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.image_id = SCP_BL2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = SCP_BL2_BASE,
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.image_info.image_max_size = SCP_BL2_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif /* SCP_BL2_BASE */
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#ifdef EL3_PAYLOAD_BASE
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/* Fill EL3 payload related information (BL31 is EL3 payload)*/
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = EL3_PAYLOAD_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#else /* EL3_PAYLOAD_BASE */
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/* Fill BL31 related information */
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
|
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},
|
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#endif /* EL3_PAYLOAD_BASE */
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{
|
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
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.image_info.image_max_size =
|
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0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET,
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
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},
|
||||
};
|
||||
|
||||
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
|
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|
|
@ -19,7 +19,7 @@
|
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#include <common/image_decompress.h>
|
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#include <plat/common/platform.h>
|
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#include <platform_def.h>
|
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#include <platform_private.h>
|
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#include <socfpga_private.h>
|
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#include <drivers/synopsys/dw_mmc.h>
|
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#include <lib/mmio.h>
|
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#include <lib/xlat_tables/xlat_tables.h>
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|
|
@ -29,7 +29,7 @@
|
|||
#include "s10_clock_manager.h"
|
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#include "s10_handoff.h"
|
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#include "s10_pinmux.h"
|
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#include "aarch64/stratix10_private.h"
|
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#include "stratix10_private.h"
|
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#include "include/s10_mailbox.h"
|
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#include "qspi/cadence_qspi.h"
|
||||
#include "wdt/watchdog.h"
|
||||
|
|
@ -78,7 +78,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
|
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console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
|
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&console);
|
||||
|
||||
plat_delay_timer_init();
|
||||
socfpga_delay_timer_init();
|
||||
init_hard_memory_controller();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,9 +21,8 @@
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_private.h>
|
||||
|
||||
#include "aarch64/stratix10_private.h"
|
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#include "stratix10_private.h"
|
||||
#include "s10_handoff.h"
|
||||
#include "s10_reset_manager.h"
|
||||
#include "s10_memory_controller.h"
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_MACROS_S__
|
||||
#define __PLAT_MACROS_S__
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below required platform porting macro
|
||||
* prints out relevant platform registers
|
||||
* whenever an unhandled exception is taken in
|
||||
* BL31.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
.endm
|
||||
|
||||
#endif /* __PLAT_MACROS_S__ */
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
|
||||
|
||||
#define PLAT_CPUID_RELEASE 0xffe1b000
|
||||
#define PLAT_S10_SEC_ENTRY 0xffe1b008
|
||||
#define PLAT_SEC_ENTRY 0xffe1b008
|
||||
|
||||
/* Define next boot image name and offset */
|
||||
#define PLAT_NS_IMAGE_OFFSET 0x50000
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PRIVATE_H__
|
||||
#define __PLATFORM_PRIVATE_H__
|
||||
#include <common/bl_common.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
void plat_configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
|
||||
|
||||
void plat_configure_mmu_el1(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
|
||||
void plat_gic_driver_init(void);
|
||||
|
||||
void plat_arm_gic_init(void);
|
||||
|
||||
void plat_delay_timer_init(void);
|
||||
|
||||
unsigned long plat_get_ns_image_entrypoint(void);
|
||||
|
||||
uint32_t plat_get_spsr_for_bl32_entry(void);
|
||||
|
||||
uint32_t plat_get_spsr_for_bl33_entry(void);
|
||||
|
||||
#endif /* __PLATFORM_PRIVATE_H__ */
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#define S10_GLOBAL_TIMER 0xffd01000
|
||||
#define S10_GLOBAL_TIMER_EN 0x3
|
||||
|
||||
/********************************************************************
|
||||
* The timer delay function
|
||||
********************************************************************/
|
||||
static uint32_t plat_get_timer_value(void)
|
||||
{
|
||||
/*
|
||||
* Generic delay timer implementation expects the timer to be a down
|
||||
* counter. We apply bitwise NOT operator to the tick values returned
|
||||
* by read_cntpct_el0() to simulate the down counter. The value is
|
||||
* clipped from 64 to 32 bits.
|
||||
*/
|
||||
return (uint32_t)(~read_cntpct_el0());
|
||||
}
|
||||
|
||||
static const timer_ops_t plat_timer_ops = {
|
||||
.get_timer_value = plat_get_timer_value,
|
||||
.clk_mult = 1,
|
||||
.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
|
||||
};
|
||||
|
||||
void plat_delay_timer_init(void)
|
||||
{
|
||||
timer_init(&plat_timer_ops);
|
||||
mmio_write_32(S10_GLOBAL_TIMER, S10_GLOBAL_TIMER_EN);
|
||||
}
|
||||
|
|
@ -15,14 +15,13 @@
|
|||
#include <lib/psci/psci.h>
|
||||
|
||||
#include "platform_def.h"
|
||||
#include "platform_private.h"
|
||||
#include "s10_reset_manager.h"
|
||||
#include "s10_mailbox.h"
|
||||
|
||||
#define S10_RSTMGR_OFST 0xffd11000
|
||||
#define S10_RSTMGR_MPUMODRST_OFST 0x20
|
||||
|
||||
uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_S10_SEC_ENTRY;
|
||||
uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
|
||||
uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include <lib/utils.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include "platform_def.h"
|
||||
#include "aarch64/stratix10_private.h"
|
||||
#include "stratix10_private.h"
|
||||
|
||||
#define STRATIX10_FIP_BASE (0)
|
||||
#define STRATIX10_FIP_MAX_SIZE (0x1000000)
|
||||
|
|
|
|||
|
|
@ -1,50 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <platform_def.h>
|
||||
#include <lib/psci/psci.h>
|
||||
static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the default topology tree information.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return plat_power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function implements a part of the critical interface between the psci
|
||||
* generic layer and the platform that allows the former to query the platform
|
||||
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
|
||||
* in case the MPIDR is invalid.
|
||||
******************************************************************************/
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
unsigned int cluster_id, cpu_id;
|
||||
|
||||
mpidr &= MPIDR_AFFINITY_MASK;
|
||||
|
||||
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
|
||||
return -1;
|
||||
|
||||
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
|
||||
if (cluster_id >= PLATFORM_CLUSTER_COUNT)
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Validate cpu_id by checking whether it represents a CPU in
|
||||
* one of the two clusters present on the platform.
|
||||
*/
|
||||
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
|
||||
return -1;
|
||||
|
||||
return (cpu_id + (cluster_id * 4));
|
||||
}
|
||||
|
||||
|
|
@ -5,9 +5,9 @@
|
|||
#
|
||||
|
||||
PLAT_INCLUDES := \
|
||||
-Iplat/intel/soc/stratix10/ \
|
||||
-Iplat/intel/soc/stratix10/include/ \
|
||||
-Iplat/intel/soc/common/drivers/
|
||||
-Iplat/intel/soc/common/drivers/ \
|
||||
-Iplat/intel/soc/common/include/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := \
|
||||
lib/xlat_tables/xlat_tables_common.c \
|
||||
|
|
@ -15,12 +15,12 @@ PLAT_BL_COMMON_SOURCES := \
|
|||
drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_main.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
plat/common/plat_gicv2.c \
|
||||
plat/common/plat_gicv2.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
plat/intel/soc/stratix10/aarch64/platform_common.c \
|
||||
plat/intel/soc/stratix10/aarch64/plat_helpers.S \
|
||||
plat/intel/soc/common/aarch64/platform_common.c \
|
||||
plat/intel/soc/common/aarch64/plat_helpers.S
|
||||
|
||||
BL2_SOURCES += \
|
||||
drivers/partition/partition.c \
|
||||
|
|
@ -35,15 +35,15 @@ BL2_SOURCES += \
|
|||
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
|
||||
plat/intel/soc/stratix10/bl2_plat_setup.c \
|
||||
plat/intel/soc/stratix10/plat_storage.c \
|
||||
plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \
|
||||
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
|
||||
plat/intel/soc/stratix10/soc/s10_reset_manager.c \
|
||||
plat/intel/soc/stratix10/soc/s10_handoff.c \
|
||||
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
|
||||
plat/intel/soc/stratix10/soc/s10_pinmux.c \
|
||||
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
|
||||
plat/intel/soc/stratix10/plat_delay_timer.c \
|
||||
plat/intel/soc/common/socfpga_delay_timer.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
plat/intel/soc/stratix10/stratix10_image_load.c \
|
||||
plat/intel/soc/common/socfpga_image_load.c \
|
||||
plat/intel/soc/stratix10/soc/s10_system_manager.c \
|
||||
common/desc_image_load.c \
|
||||
plat/intel/soc/stratix10/soc/s10_mailbox.c \
|
||||
|
|
@ -58,13 +58,13 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
|
|||
plat/intel/soc/stratix10/plat_sip_svc.c \
|
||||
plat/intel/soc/stratix10/bl31_plat_setup.c \
|
||||
plat/intel/soc/stratix10/plat_psci.c \
|
||||
plat/intel/soc/stratix10/plat_topology.c \
|
||||
plat/intel/soc/stratix10/plat_delay_timer.c \
|
||||
plat/intel/soc/common/socfpga_topology.c \
|
||||
plat/intel/soc/common/socfpga_delay_timer.c \
|
||||
plat/intel/soc/stratix10/soc/s10_reset_manager.c\
|
||||
plat/intel/soc/stratix10/soc/s10_pinmux.c \
|
||||
plat/intel/soc/stratix10/soc/s10_clock_manager.c\
|
||||
plat/intel/soc/stratix10/soc/s10_handoff.c \
|
||||
plat/intel/soc/stratix10/soc/s10_mailbox.c \
|
||||
plat/intel/soc/stratix10/soc/s10_mailbox.c
|
||||
|
||||
PROGRAMMABLE_RESET_ADDRESS := 0
|
||||
BL2_AT_EL3 := 1
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@
|
|||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_private.h>
|
||||
|
||||
#include "s10_clock_manager.h"
|
||||
#include "s10_handoff.h"
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
#include <string.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_private.h>
|
||||
|
||||
#include "s10_handoff.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <lib/mmio.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_private.h>
|
||||
#include "s10_reset_manager.h"
|
||||
|
||||
void deassert_peripheral_reset(void)
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/desc_image_load.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* This function flushes the data structures so that they are visible
|
||||
* in memory for the next BL image.
|
||||
******************************************************************************/
|
||||
void plat_flush_next_bl_params(void)
|
||||
{
|
||||
flush_bl_params_desc();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the list of loadable images.
|
||||
******************************************************************************/
|
||||
bl_load_info_t *plat_get_bl_image_load_info(void)
|
||||
{
|
||||
return get_bl_load_info_from_mem_params_desc();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the list of executable images.
|
||||
******************************************************************************/
|
||||
bl_params_t *plat_get_next_bl_params(void)
|
||||
{
|
||||
return get_next_bl_params_from_mem_params_desc();
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue