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9d82ef26c6
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/desc_image_load.h>
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/*******************************************************************************
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* This function flushes the data structures so that they are visible
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* in memory for the next BL image.
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******************************************************************************/
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void plat_flush_next_bl_params(void)
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{
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flush_bl_params_desc();
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}
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/*******************************************************************************
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* This function returns the list of loadable images.
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******************************************************************************/
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bl_load_info_t *plat_get_bl_image_load_info(void)
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{
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return get_bl_load_info_from_mem_params_desc();
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}
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/*******************************************************************************
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* This function returns the list of executable images.
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******************************************************************************/
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bl_params_t *plat_get_next_bl_params(void)
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{
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return get_next_bl_params_from_mem_params_desc();
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}
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