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https://github.com/ARM-software/arm-trusted-firmware.git
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9d82ef26c6
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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unsigned int plat_get_syscnt_freq2(void)
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{
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return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return PLAT_NS_IMAGE_OFFSET;
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}
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/******************************************************************************
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* Gets SPSR for BL32 entry
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*****************************************************************************/
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uint32_t plat_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/******************************************************************************
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* Gets SPSR for BL33 entry
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*****************************************************************************/
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uint32_t plat_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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