mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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feat(mt8188): add armv8.2 support
Add armv8.2 support for MT8188. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Change-Id: I0ac865949ba864fb207ee1f0937092cbabd550de
This commit is contained in:
Edward-JW Yang
Bo-Chen Chen
parent
7079a942bd
commit
45711e4e16
10 changed files with 215 additions and 145 deletions
118
plat/mediatek/helpers/armv8_2/arch_helpers.S
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118
plat/mediatek/helpers/armv8_2/arch_helpers.S
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@ -0,0 +1,118 @@
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/*
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* Copyright (c) 2022, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#if CONFIG_MTK_MCUSYS
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#include <mcucfg.h>
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#endif
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#include <platform_def.h>
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/*
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* Declare as weak function so that can be
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* overwritten by platform helpers
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*/
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.weak platform_mem_init
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.weak plat_core_pos_by_mpidr
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.weak plat_my_core_pos
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.weak plat_mediatek_calc_core_pos
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.global plat_mpidr_by_core_pos
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.global plat_reset_handler
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/* -----------------------------------------------------
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* unsigned long plat_mpidr_by_core_pos(uint32_t cpuid)
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* This function calcuate mpidr by cpu pos if cpu
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* topology is linear.
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*
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* Clobbers: x0-x1
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* -----------------------------------------------------
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*/
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func plat_mpidr_by_core_pos
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lsl x0, x0, #MPIDR_AFF1_SHIFT
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mrs x1, mpidr_el1
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and x1, x1, #MPIDR_MT_MASK
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orr x0, x0, x1
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ret
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endfunc plat_mpidr_by_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_arm_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_mediatek_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* int plat_mediatek_calc_core_pos(u_register_t mpidr);
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*
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* In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
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* AFF0 is thread id. There is only one cluster in ARMv8.2
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* and one thread in current implementation.
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*
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* With this function: CorePos = CoreID (AFF1)
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* we do it with x0 = (x0 >> 8) & 0xff
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* -----------------------------------------------------
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*/
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func plat_mediatek_calc_core_pos
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b plat_core_pos_by_mpidr
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endfunc plat_mediatek_calc_core_pos
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/* ------------------------------------------------------
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* int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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*
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* This function implements a part of the critical
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* interface between the psci generic layer and the
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* platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index.
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*
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* Clobbers: x0-x1
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* ------------------------------------------------------
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*/
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func plat_core_pos_by_mpidr
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mov x1, #MPIDR_AFFLVL_MASK
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and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
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ret
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endfunc plat_core_pos_by_mpidr
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func plat_reset_handler
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#if CONFIG_MTK_MCUSYS
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mov x10, x30
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bl plat_my_core_pos
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mov x30, x10
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mov w1, #0x1
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lsl w1, w1, w0
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ldr x0, =CPC_MCUSYS_CPU_ON_SW_HINT_SET
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str w1, [x0]
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dsb sy
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#endif
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#if CONFIG_MTK_ECC
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mov x10, x30
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/* enable sequence of ecc for cpus */
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bl disable_core_ecc
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bl ft_ecc_clear_per_core
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bl enable_core_ecc
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mov x30, x10
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#endif
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ret
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endfunc plat_reset_handler
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12
plat/mediatek/helpers/rules.mk
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12
plat/mediatek/helpers/rules.mk
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@ -0,0 +1,12 @@
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#
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# Copyright (c) 2022, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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LOCAL_DIR := $(call GET_LOCAL_DIR)
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MODULE := helpers
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LOCAL_SRCS-y += $(LOCAL_DIR)/$(ARCH_VERSION)/arch_helpers.S
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$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
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38
plat/mediatek/include/armv8_2/arch_def.h
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38
plat/mediatek/include/armv8_2/arch_def.h
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2022, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARCH_DEF_H
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#define ARCH_DEF_H
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/* Topology constants */
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#define PLAT_MAX_PWR_LVL (2)
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#define PLAT_MAX_RET_STATE (1)
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#define PLAT_MAX_OFF_STATE (2)
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#define PLATFORM_SYSTEM_COUNT (1)
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#define PLATFORM_CLUSTER_COUNT (1)
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#define PLATFORM_CLUSTER0_CORE_COUNT (8)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER (8)
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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/* Cachline size */
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#define CACHE_WRITEBACK_SHIFT (6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* ARCH_DEF_H */
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@ -7,6 +7,8 @@
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch_def.h>
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#define PLAT_PRIMARY_CPU (0x0)
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#define MT_GIC_BASE (0x0C000000)
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@ -124,22 +126,7 @@
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* Generic platform constants
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******************************************************************************/
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#define PLATFORM_STACK_SIZE (0x800)
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLAT_MAX_PWR_LVL U(3)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(9)
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_MCUSYS_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
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#define SOC_CHIP_ID U(0x8188)
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/*******************************************************************************
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@ -167,16 +154,4 @@
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#define MAX_XLAT_TABLES (16)
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#define MAX_MMAP_REGIONS (16)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT (6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* PLATFORM_DEF_H */
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@ -1,45 +0,0 @@
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/*
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* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_mediatek_calc_core_pos
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_mediatek_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_mediatek_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
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*
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* With this function: CorePos = CoreID (AFF1)
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* we do it with x0 = (x0 >> 8) & 0xff
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* -----------------------------------------------------
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*/
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func plat_mediatek_calc_core_pos
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mov x1, #MPIDR_AFFLVL_MASK
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and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
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ret
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endfunc plat_mediatek_calc_core_pos
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@ -32,5 +32,6 @@ ERRATA_A78_2242635 := 1
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ERRATA_A78_2376745 := 1
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ERRATA_A78_2395406 := 1
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CONFIG_ARCH_ARM_V8_2 := y
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MACH_MT8188 := 1
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$(eval $(call add_define,MACH_MT8188))
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@ -1,70 +0,0 @@
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/*
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* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/psci/psci.h>
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#include <plat_helpers.h>
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#include <platform_def.h>
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const unsigned char mtk_power_domain_tree_desc[] = {
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/* Number of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* Number of children for the root node */
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PLATFORM_MCUSYS_COUNT,
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/* Number of children for the mcusys node */
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PLATFORM_CLUSTER_COUNT,
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/* Number of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return mtk_power_domain_tree_desc;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id;
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if ((read_mpidr() & MPIDR_MT_MASK) != 0) {
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/* ARMv8.2 arch */
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if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) {
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return -1;
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}
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return plat_mediatek_calc_core_pos(mpidr);
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}
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mpidr &= MPIDR_AFFINITY_MASK;
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if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) {
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return -1;
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}
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
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if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
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return -1;
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}
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/*
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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*/
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
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return -1;
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}
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return (cpu_id + (cluster_id * 8));
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}
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@ -15,6 +15,7 @@ include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_INCLUDES := -I${MTK_PLAT}/common \
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-I${MTK_PLAT}/include \
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-I${MTK_PLAT}/include/${MTK_SOC} \
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-I${MTK_PLAT}/include/${ARCH_VERSION} \
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-I${MTK_PLAT} \
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-I${MTK_PLAT_SOC}/include \
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-Idrivers/arm/gic \
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@ -36,6 +37,8 @@ MODULES-y += $(MTK_PLAT)/drivers/pmic
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MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
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MODULES-y += $(MTK_PLAT)/drivers/rtc
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MODULES-y += $(MTK_PLAT)/drivers/timer
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MODULES-y += $(MTK_PLAT)/helpers
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MODULES-y += $(MTK_PLAT)/topology
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PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
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drivers/ti/uart/aarch64/16550_console.S \
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@ -52,9 +55,7 @@ BL31_SOURCES += drivers/delay_timer/delay_timer.c \
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plat/common/aarch64/crash_console_helpers.S \
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${MTK_PLAT}/common/mtk_plat_common.c \
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${MTK_PLAT}/common/params_setup.c \
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${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
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$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c \
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$(MTK_PLAT)/$(MTK_SOC)/plat_topology.c
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$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c
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include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
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28
plat/mediatek/topology/armv8_2/topology.c
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28
plat/mediatek/topology/armv8_2/topology.c
Normal file
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/*
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* Copyright (c) 2022, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <lib/psci/psci.h>
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#include <platform_def.h>
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#pragma weak plat_get_power_domain_tree_desc
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static const unsigned char mtk_power_domain_tree_desc[] = {
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/* Number of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* Number of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* Number of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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/*******************************************************************************
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* This function returns the default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return mtk_power_domain_tree_desc;
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}
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12
plat/mediatek/topology/rules.mk
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12
plat/mediatek/topology/rules.mk
Normal file
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@ -0,0 +1,12 @@
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#
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# Copyright (c) 2022, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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LOCAL_DIR := $(call GET_LOCAL_DIR)
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MODULE := topology
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LOCAL_SRCS-y := $(LOCAL_DIR)/$(ARCH_VERSION)/topology.c
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$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
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