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https://github.com/ARM-software/arm-trusted-firmware.git
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45711e4e16
Add armv8.2 support for MT8188. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Change-Id: I0ac865949ba864fb207ee1f0937092cbabd550de
38 lines
1.4 KiB
C
38 lines
1.4 KiB
C
/*
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* Copyright (c) 2022, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARCH_DEF_H
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#define ARCH_DEF_H
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/* Topology constants */
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#define PLAT_MAX_PWR_LVL (2)
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#define PLAT_MAX_RET_STATE (1)
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#define PLAT_MAX_OFF_STATE (2)
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#define PLATFORM_SYSTEM_COUNT (1)
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#define PLATFORM_CLUSTER_COUNT (1)
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#define PLATFORM_CLUSTER0_CORE_COUNT (8)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER (8)
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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/* Cachline size */
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#define CACHE_WRITEBACK_SHIFT (6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* ARCH_DEF_H */
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