mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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feat(mt8188): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. TEST=build pass. BUG=b:244216434 Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com> Change-Id: I468036131e941a46bc1ec12d33105146000730d8
This commit is contained in:
Fengquan Chen
Bo-Chen Chen
parent
8454f0d65e
commit
7079a942bd
8 changed files with 242 additions and 0 deletions
43
plat/mediatek/drivers/dfd/dfd.c
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43
plat/mediatek/drivers/dfd/dfd.c
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@ -0,0 +1,43 @@
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <dfd.h>
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#include <mtk_sip_svc.h>
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#include <plat_dfd.h>
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static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3,
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void *handle, struct smccc_res *smccc_ret)
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{
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int ret = MTK_SIP_E_SUCCESS;
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switch (arg0) {
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case PLAT_MTK_DFD_SETUP_MAGIC:
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INFO("[%s] DFD setup call from kernel\n", __func__);
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dfd_setup(arg1, arg2, arg3);
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break;
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case PLAT_MTK_DFD_READ_MAGIC:
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/* only allow to access DFD register base + 0x200 */
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if (arg1 <= 0x200) {
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ret = mmio_read_32(MISC1_CFG_BASE + arg1);
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}
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break;
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case PLAT_MTK_DFD_WRITE_MAGIC:
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/* only allow to access DFD register base + 0x200 */
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if (arg1 <= 0x200) {
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sync_writel(MISC1_CFG_BASE + arg1, arg2);
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}
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break;
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default:
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ret = MTK_SIP_E_INVALID_PARAM;
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break;
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}
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return ret;
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}
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DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_DFD, dfd_smc_dispatcher);
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16
plat/mediatek/drivers/dfd/dfd.h
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16
plat/mediatek/drivers/dfd/dfd.h
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DFD_H
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#define DFD_H
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#include <arch_helpers.h>
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#include <lib/mmio.h>
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void dfd_resume(void);
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void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump);
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#endif /* DFD_H */
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82
plat/mediatek/drivers/dfd/mt8188/plat_dfd.c
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82
plat/mediatek/drivers/dfd/mt8188/plat_dfd.c
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@ -0,0 +1,82 @@
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <dfd.h>
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#include <plat_dfd.h>
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static uint64_t dfd_cache_dump;
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static bool dfd_enabled;
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static uint64_t dfd_base_addr;
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static uint64_t dfd_chain_length;
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void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump)
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{
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mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL);
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mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL);
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mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL);
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mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, BIT(2));
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mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1);
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sync_writel(DFD_INTERNAL_CTL, 0x5);
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mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13));
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
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mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
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mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
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mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
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mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
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mmio_write_32(DFD_TEST_SI_0, 0x0);
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mmio_write_32(DFD_TEST_SI_1, 0x0);
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mmio_write_32(DFD_TEST_SI_2, 0x0);
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mmio_write_32(DFD_TEST_SI_3, 0x0);
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sync_writel(DFD_POWER_CTL, 0xF9);
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sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL);
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sync_writel(DFD_V30_CTL, 0xD);
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mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
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mmio_write_32(DFD_O_REG_0, 0);
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/* setup global variables for suspend and resume */
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dfd_enabled = true;
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dfd_base_addr = base_addr;
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dfd_chain_length = chain_length;
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dfd_cache_dump = cache_dump;
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if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
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mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL);
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sync_writel(DFD_V35_ENABLE, 0x1);
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sync_writel(DFD_V35_TAP_NUMBER, 0xB);
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sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
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sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
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/* Cache dump only mode */
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sync_writel(DFD_V35_CTL, 0x1);
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mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF);
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mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL);
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mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL);
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mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL);
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mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL);
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if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) {
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sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
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}
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}
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dsbsy();
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}
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void dfd_resume(void)
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{
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if (dfd_enabled == true) {
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dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
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}
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}
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78
plat/mediatek/drivers/dfd/mt8188/plat_dfd.h
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78
plat/mediatek/drivers/dfd/mt8188/plat_dfd.h
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_DFD_H
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#define PLAT_DFD_H
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#include <lib/mmio.h>
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#include <platform_def.h>
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#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0)
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#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
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#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
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#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
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#define MTK_DRM_LATCH_CTL1 (DRM_BASE + 0x40)
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#define MTK_DRM_LATCH_CTL2 (DRM_BASE + 0x44)
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#define MTK_WDT_BASE (RGU_BASE)
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#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10)
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#define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48)
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#define MCU_BIU_BASE (MCUCFG_BASE)
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#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
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#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
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#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
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#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
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#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
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#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
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#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)
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#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)
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#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
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#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
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#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34)
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#define DFD_INTERNAL_SW_NS_TRIGGER (MISC1_CFG_BASE + 0x3c)
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#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
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#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
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#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
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#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
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#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
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#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60)
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#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
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#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)
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#define DFD_READ_ADDR (MISC1_CFG_BASE + 0x1E8)
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#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)
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#define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8)
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#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
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#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
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#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
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#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
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#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
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#define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC)
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#define DFD_O_PROTECT_EN_REG (0x10001220)
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#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C)
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#define DFD_O_SET_BASEADDR_REG (0x10043000)
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#define DFD_O_REG_0 (0x10001390)
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#define DFD_CACHE_DUMP_ENABLE (1U)
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#define DFD_PARITY_ERR_TRIGGER (2U)
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#define DFD_V35_TAP_EN_VAL (0x43FF)
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#define DFD_V35_SEQ0_0_VAL (0x63668820)
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#define DFD_READ_ADDR_VAL (0x40000008)
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#define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF)
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#define MTK_WDT_LATCH_CTL2_VAL (0x9507FFFF)
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#define MTK_WDT_INTERVAL_VAL (0x6600000A)
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#define MTK_DRM_LATCH_CTL2_VAL (0x950607D0)
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#define MTK_DRM_LATCH_CTL2_CACHE_VAL (0x95065DC0)
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#define MTK_DRM_LATCH_CTL1_VAL (0x95000013)
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#endif /* PLAT_DFD_H */
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17
plat/mediatek/drivers/dfd/rules.mk
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plat/mediatek/drivers/dfd/rules.mk
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#
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# Copyright (c) 2022, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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LOCAL_DIR := $(call GET_LOCAL_DIR)
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MODULE := mtk_dfd
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LOCAL_SRCS-y := ${LOCAL_DIR}/dfd.c
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LOCAL_SRCS-y += ${LOCAL_DIR}/$(MTK_SOC)/plat_dfd.c
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PLAT_INCLUDES += -I${LOCAL_DIR}
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PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC)
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$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
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* GPIO related constants
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******************************************************************************/
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#define GPIO_BASE (IO_PHYS + 0x00005000)
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#define RGU_BASE (IO_PHYS + 0x00007000)
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#define DRM_BASE (IO_PHYS + 0x0000D000)
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#define IOCFG_RM_BASE (IO_PHYS + 0x01C00000)
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#define IOCFG_LT_BASE (IO_PHYS + 0x01E10000)
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#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
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@ -17,6 +17,7 @@
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <dfd.h>
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#include <lib/mtk_init/mtk_init.h>
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#include <lib/pm/mtk_pm.h>
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#include <mt_gic_v3.h>
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@ -106,6 +107,8 @@ static void armv8_2_mcusys_pwr_on_common(const struct mtk_cpupm_pwrstate *state)
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mt_gic_distif_restore();
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gic_sgi_restore_all();
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dfd_resume();
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/* Add code here that behavior before system enter mcusys'on */
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_MCUSYS)) {
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mtk_cpu_pwr.ops->mcusys_resume(state);
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@ -25,6 +25,7 @@ MODULES-y += $(MTK_PLAT)/lib/pm
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MODULES-y += $(MTK_PLAT)/lib/system_reset
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MODULES-y += $(MTK_PLAT)/drivers/cirq
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MODULES-y += $(MTK_PLAT)/drivers/dcm
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MODULES-y += $(MTK_PLAT)/drivers/dfd
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MODULES-y += $(MTK_PLAT)/drivers/dp
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MODULES-y += $(MTK_PLAT)/drivers/emi_mpu
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MODULES-y += $(MTK_PLAT)/drivers/gic600
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