From 7079a942bd9705fd9e0cd220324f7dfd9c53dcad Mon Sep 17 00:00:00 2001 From: Fengquan Chen Date: Wed, 17 Aug 2022 10:42:15 +0800 Subject: [PATCH] feat(mt8188): add DFD control in SiP service DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. TEST=build pass. BUG=b:244216434 Signed-off-by: Fengquan Chen Change-Id: I468036131e941a46bc1ec12d33105146000730d8 --- plat/mediatek/drivers/dfd/dfd.c | 43 +++++++++++ plat/mediatek/drivers/dfd/dfd.h | 16 ++++ plat/mediatek/drivers/dfd/mt8188/plat_dfd.c | 82 +++++++++++++++++++++ plat/mediatek/drivers/dfd/mt8188/plat_dfd.h | 78 ++++++++++++++++++++ plat/mediatek/drivers/dfd/rules.mk | 17 +++++ plat/mediatek/include/mt8188/platform_def.h | 2 + plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c | 3 + plat/mediatek/mt8188/platform.mk | 1 + 8 files changed, 242 insertions(+) create mode 100644 plat/mediatek/drivers/dfd/dfd.c create mode 100644 plat/mediatek/drivers/dfd/dfd.h create mode 100644 plat/mediatek/drivers/dfd/mt8188/plat_dfd.c create mode 100644 plat/mediatek/drivers/dfd/mt8188/plat_dfd.h create mode 100644 plat/mediatek/drivers/dfd/rules.mk diff --git a/plat/mediatek/drivers/dfd/dfd.c b/plat/mediatek/drivers/dfd/dfd.c new file mode 100644 index 000000000..5770d5014 --- /dev/null +++ b/plat/mediatek/drivers/dfd/dfd.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#include + +static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3, + void *handle, struct smccc_res *smccc_ret) +{ + int ret = MTK_SIP_E_SUCCESS; + + switch (arg0) { + case PLAT_MTK_DFD_SETUP_MAGIC: + INFO("[%s] DFD setup call from kernel\n", __func__); + dfd_setup(arg1, arg2, arg3); + break; + case PLAT_MTK_DFD_READ_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + ret = mmio_read_32(MISC1_CFG_BASE + arg1); + } + break; + case PLAT_MTK_DFD_WRITE_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + sync_writel(MISC1_CFG_BASE + arg1, arg2); + } + break; + default: + ret = MTK_SIP_E_INVALID_PARAM; + break; + } + + return ret; +} +DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_DFD, dfd_smc_dispatcher); diff --git a/plat/mediatek/drivers/dfd/dfd.h b/plat/mediatek/drivers/dfd/dfd.h new file mode 100644 index 000000000..c088bd0ef --- /dev/null +++ b/plat/mediatek/drivers/dfd/dfd.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DFD_H +#define DFD_H + +#include +#include + +void dfd_resume(void); +void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump); + +#endif /* DFD_H */ diff --git a/plat/mediatek/drivers/dfd/mt8188/plat_dfd.c b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.c new file mode 100644 index 000000000..1aa68f534 --- /dev/null +++ b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include + +static uint64_t dfd_cache_dump; +static bool dfd_enabled; +static uint64_t dfd_base_addr; +static uint64_t dfd_chain_length; + +void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump) +{ + mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); + mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); + mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); + + mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, BIT(2)); + mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); + sync_writel(DFD_INTERNAL_CTL, 0x5); + mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); + + mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); + mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); + mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); + mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); + + mmio_write_32(DFD_TEST_SI_0, 0x0); + mmio_write_32(DFD_TEST_SI_1, 0x0); + mmio_write_32(DFD_TEST_SI_2, 0x0); + mmio_write_32(DFD_TEST_SI_3, 0x0); + + sync_writel(DFD_POWER_CTL, 0xF9); + sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); + sync_writel(DFD_V30_CTL, 0xD); + + mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); + mmio_write_32(DFD_O_REG_0, 0); + + /* setup global variables for suspend and resume */ + dfd_enabled = true; + dfd_base_addr = base_addr; + dfd_chain_length = chain_length; + dfd_cache_dump = cache_dump; + + if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { + mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL); + sync_writel(DFD_V35_ENABLE, 0x1); + sync_writel(DFD_V35_TAP_NUMBER, 0xB); + sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); + sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); + + /* Cache dump only mode */ + sync_writel(DFD_V35_CTL, 0x1); + mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF); + mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL); + mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL); + mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL); + mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL); + + if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) { + sync_writel(DFD_HW_TRIGGER_MASK, 0xC); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); + } + } + dsbsy(); +} + +void dfd_resume(void) +{ + if (dfd_enabled == true) { + dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); + } +} diff --git a/plat/mediatek/drivers/dfd/mt8188/plat_dfd.h b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.h new file mode 100644 index 000000000..5b98024a4 --- /dev/null +++ b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DFD_H +#define PLAT_DFD_H + +#include +#include + +#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0) + +#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) +#define PLAT_MTK_DFD_READ_MAGIC (0x99716151) +#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) + +#define MTK_DRM_LATCH_CTL1 (DRM_BASE + 0x40) +#define MTK_DRM_LATCH_CTL2 (DRM_BASE + 0x44) + +#define MTK_WDT_BASE (RGU_BASE) +#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10) +#define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48) + +#define MCU_BIU_BASE (MCUCFG_BASE) +#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) +#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) +#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08) +#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C) +#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10) +#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C) +#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20) +#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24) +#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28) +#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30) +#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34) +#define DFD_INTERNAL_SW_NS_TRIGGER (MISC1_CFG_BASE + 0x3c) +#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48) +#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C) +#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50) +#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58) +#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C) +#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60) +#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8) +#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC) +#define DFD_READ_ADDR (MISC1_CFG_BASE + 0x1E8) +#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC) + +#define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8) +#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC) +#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0) +#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4) +#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0) +#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4) +#define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC) + +#define DFD_O_PROTECT_EN_REG (0x10001220) +#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C) +#define DFD_O_SET_BASEADDR_REG (0x10043000) +#define DFD_O_REG_0 (0x10001390) + +#define DFD_CACHE_DUMP_ENABLE (1U) +#define DFD_PARITY_ERR_TRIGGER (2U) + +#define DFD_V35_TAP_EN_VAL (0x43FF) +#define DFD_V35_SEQ0_0_VAL (0x63668820) +#define DFD_READ_ADDR_VAL (0x40000008) +#define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF) + +#define MTK_WDT_LATCH_CTL2_VAL (0x9507FFFF) +#define MTK_WDT_INTERVAL_VAL (0x6600000A) +#define MTK_DRM_LATCH_CTL2_VAL (0x950607D0) +#define MTK_DRM_LATCH_CTL2_CACHE_VAL (0x95065DC0) + +#define MTK_DRM_LATCH_CTL1_VAL (0x95000013) + +#endif /* PLAT_DFD_H */ diff --git a/plat/mediatek/drivers/dfd/rules.mk b/plat/mediatek/drivers/dfd/rules.mk new file mode 100644 index 000000000..60fbc88df --- /dev/null +++ b/plat/mediatek/drivers/dfd/rules.mk @@ -0,0 +1,17 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtk_dfd + +LOCAL_SRCS-y := ${LOCAL_DIR}/dfd.c +LOCAL_SRCS-y += ${LOCAL_DIR}/$(MTK_SOC)/plat_dfd.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC) + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/include/mt8188/platform_def.h b/plat/mediatek/include/mt8188/platform_def.h index aed5ee592..023483740 100644 --- a/plat/mediatek/include/mt8188/platform_def.h +++ b/plat/mediatek/include/mt8188/platform_def.h @@ -23,6 +23,8 @@ * GPIO related constants ******************************************************************************/ #define GPIO_BASE (IO_PHYS + 0x00005000) +#define RGU_BASE (IO_PHYS + 0x00007000) +#define DRM_BASE (IO_PHYS + 0x0000D000) #define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) #define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) diff --git a/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c b/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c index 88e2a1406..7ffc4edab 100644 --- a/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c +++ b/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -106,6 +107,8 @@ static void armv8_2_mcusys_pwr_on_common(const struct mtk_cpupm_pwrstate *state) mt_gic_distif_restore(); gic_sgi_restore_all(); + dfd_resume(); + /* Add code here that behavior before system enter mcusys'on */ if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_MCUSYS)) { mtk_cpu_pwr.ops->mcusys_resume(state); diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk index 11e75e85a..4233d920a 100644 --- a/plat/mediatek/mt8188/platform.mk +++ b/plat/mediatek/mt8188/platform.mk @@ -25,6 +25,7 @@ MODULES-y += $(MTK_PLAT)/lib/pm MODULES-y += $(MTK_PLAT)/lib/system_reset MODULES-y += $(MTK_PLAT)/drivers/cirq MODULES-y += $(MTK_PLAT)/drivers/dcm +MODULES-y += $(MTK_PLAT)/drivers/dfd MODULES-y += $(MTK_PLAT)/drivers/dp MODULES-y += $(MTK_PLAT)/drivers/emi_mpu MODULES-y += $(MTK_PLAT)/drivers/gic600