feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM functionality. Enable wakeup for
new peripherals

Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

plat/amd/versal2/include/plat_pm_common.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,4 +22,17 @@
 #define NON_SECURE_FLAG		1U
 #define SECURE_FLAG		0U
 
+/* Processor core device IDs */
+#define PM_DEV_CLUSTER0_ACPU_0	(0x1810C0AFU)
+#define PM_DEV_CLUSTER0_ACPU_1	(0x1810C0B0U)
+
+#define PM_DEV_CLUSTER1_ACPU_0	(0x1810C0B3U)
+#define PM_DEV_CLUSTER1_ACPU_1	(0x1810C0B4U)
+
+#define PM_DEV_CLUSTER2_ACPU_0	(0x1810C0B7U)
+#define PM_DEV_CLUSTER2_ACPU_1	(0x1810C0B8U)
+
+#define PM_DEV_CLUSTER3_ACPU_0	(0x1810C0BBU)
+#define PM_DEV_CLUSTER3_ACPU_1	(0x1810C0BCU)
+
 #endif /* PLAT_PM_COMMON_H */

plat/amd/versal2/include/plat_private.h

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,7 +45,7 @@ extern uint32_t rtlversion, psversion, pmcversion;
 void board_detection(void);
 const char *board_name_decode(void);
 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
-		       uint64_t x4, void *cookie, void *handle, uint64_t flags);
+		       uint64_t x4, const void *cookie, void *handle, uint64_t flags);
 int32_t sip_svc_setup_init(void);
 /*
  * Register handler to specific GIC entrance

plat/amd/versal2/include/platform_def.h

@@ -11,6 +11,7 @@
 
 #include <arch.h>
 #include "def.h"
+#include <plat_common.h>
 
 /*******************************************************************************
  * Generic platform constants
@@ -140,6 +141,8 @@
 #define PLAT_G0_IRQ_PROPS(grp) \
 	INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE)
 
 #define IRQ_MAX		200U
 

plat/amd/versal2/plat_psci.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -200,7 +200,7 @@ static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id,
 }
 
 static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
-			      uint64_t x4, void *cookie, void *handle, uint64_t flags)
+			      uint64_t x4, const void *cookie, void *handle, uint64_t flags)
 {
 	int32_t ret;
 	uint32_t arg[4], api_id;
@@ -240,7 +240,7 @@ static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64
 }
 
 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
-		     void *cookie, void *handle, uint64_t flags)
+		     const void *cookie, void *handle, uint64_t flags)
 {
 	return no_pm_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
 }

plat/amd/versal2/plat_psci_pm.c

@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <plat_arm.h>
+
+#include "def.h"
+#include <ipi.h>
+#include <plat_private.h>
+#include "pm_api_sys.h"
+#include "pm_client.h"
+#include <pm_common.h>
+#include "pm_defs.h"
+#include "pm_svc_main.h"
+
+static uintptr_t sec_entry;
+
+static int32_t versal2_pwr_domain_on(u_register_t mpidr)
+{
+	int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
+	int32_t ret = (int32_t) PSCI_E_INTERN_FAIL;
+	enum pm_ret_status pm_ret;
+	const struct pm_proc *proc;
+
+	if (cpu_id != -1) {
+		proc = pm_get_proc((uint32_t)cpu_id);
+		if (proc != NULL) {
+			pm_ret = pm_req_wakeup(proc->node_id,
+					       (uint32_t)
+					       ((sec_entry & 0xFFFFFFFFU) | 0x1U),
+					       sec_entry >> 32, 0, 0);
+
+			if (pm_ret == PM_RET_SUCCESS) {
+				/* Clear power down request */
+				pm_client_wakeup(proc);
+				ret = (int32_t) PSCI_E_SUCCESS;
+			}
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * versal2_pwr_domain_off() - Turn off core.
+ * @target_state: Targeted state.
+ */
+static void versal2_pwr_domain_off(const psci_power_state_t *target_state)
+{
+	const struct pm_proc *proc;
+	uint32_t cpu_id = plat_my_core_pos();
+	enum pm_ret_status pm_ret;
+	size_t i;
+
+	proc = pm_get_proc(cpu_id);
+	if (proc == NULL) {
+		ERROR("Failed to get proc %d\n", cpu_id);
+		goto err;
+	}
+
+	for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
+		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
+			__func__, i, target_state->pwr_domain_state[i]);
+	}
+
+	plat_gic_cpuif_disable();
+	/*
+	 * Send request to PMC to power down the appropriate APU CPU
+	 * core.
+	 * According to PSCI specification, CPU_off function does not
+	 * have resume address and CPU core can only be woken up
+	 * invoking CPU_on function, during which resume address will
+	 * be set.
+	 */
+	pm_ret = pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
+			      SECURE_FLAG);
+
+	if (pm_ret != PM_RET_SUCCESS) {
+		ERROR("Failed to power down CPU %d\n", cpu_id);
+	}
+err:
+	return;
+}
+
+/**
+ * versal2_system_reset() - Send the reset request to firmware for the
+ *                          system to reset. This function does not
+ *                          return as it resets system.
+ */
+static void __dead2 versal2_system_reset(void)
+{
+	uint32_t timeout = 10000U;
+	enum pm_ret_status pm_ret;
+	int32_t ret;
+
+	request_cpu_pwrdwn();
+
+	/*
+	 * Send the system reset request to the firmware if power down request
+	 * is not received from firmware.
+	 */
+	if (pwrdwn_req_received == true) {
+		/*
+		 * TODO: shutdown scope for this reset needs be revised once
+		 * we have a clearer understanding of the overall reset scoping
+		 * including the implementation of SYSTEM_RESET2.
+		 */
+		pm_ret = pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
+					 pm_get_shutdown_scope(), SECURE_FLAG);
+
+		if (pm_ret != PM_RET_SUCCESS) {
+			WARN("System shutdown failed\n");
+		}
+
+		/*
+		 * Wait for system shutdown request completed and idle callback
+		 * not received.
+		 */
+		do {
+			ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id,
+						    primary_proc->ipi->remote_ipi_id);
+			udelay(100);
+			timeout--;
+		} while ((ret != (int32_t)IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U));
+	}
+
+	(void)psci_cpu_off();
+
+	while (true) {
+		wfi();
+	}
+}
+
+/**
+ * versal2_pwr_domain_suspend() - Send request to PMC to suspend core.
+ * @target_state: Targeted state.
+ */
+static void versal2_pwr_domain_suspend(const psci_power_state_t *target_state)
+{
+	const struct pm_proc *proc;
+	uint32_t cpu_id = plat_my_core_pos();
+	uint32_t state;
+	enum pm_ret_status ret;
+	size_t i;
+
+	proc = pm_get_proc(cpu_id);
+	if (proc == NULL) {
+		ERROR("Failed to get proc %d\n", cpu_id);
+		goto err;
+	}
+
+	for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
+		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
+			__func__, i, target_state->pwr_domain_state[i]);
+	}
+
+	plat_gic_cpuif_disable();
+
+	if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
+		plat_gic_save();
+	}
+
+	state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ?
+		PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
+
+	/* Send request to PMC to suspend this core */
+	ret = pm_self_suspend(proc->node_id, MAX_LATENCY, state, sec_entry,
+			      SECURE_FLAG);
+
+	if (ret != PM_RET_SUCCESS) {
+		ERROR("Failed to power down CPU %d\n", cpu_id);
+	}
+
+err:
+	return;
+}
+
+static void versal2_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+	(void)target_state;
+
+	/* Enable the gic cpu interface */
+	plat_gic_pcpu_init();
+
+	/* Program the gic per-cpu distributor or re-distributor interface */
+	plat_gic_cpuif_enable();
+}
+
+/**
+ * versal2_pwr_domain_suspend_finish() - Performs actions to finish
+ *                                       suspend procedure.
+ * @target_state: Targeted state.
+ */
+static void versal2_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
+{
+	const struct pm_proc *proc;
+	uint32_t cpu_id = plat_my_core_pos();
+	size_t i;
+
+	proc = pm_get_proc(cpu_id);
+	if (proc == NULL) {
+		ERROR("Failed to get proc %d\n", cpu_id);
+		goto err;
+	}
+
+	for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
+		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
+			__func__, i, target_state->pwr_domain_state[i]);
+	}
+
+	/* Clear the APU power control register for this cpu */
+	pm_client_wakeup(proc);
+
+	/* APU was turned off, so restore GIC context */
+	if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
+		plat_gic_resume();
+	}
+
+	plat_gic_cpuif_enable();
+
+err:
+	return;
+}
+
+/**
+ * versal2_system_off() - Send the system off request to firmware.
+ *                        This function does not return as it puts core into WFI
+ */
+static void __dead2 versal2_system_off(void)
+{
+	enum pm_ret_status ret;
+
+	/* Send the power down request to the PMC */
+	ret = pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
+				 pm_get_shutdown_scope(), SECURE_FLAG);
+
+	if (ret != PM_RET_SUCCESS) {
+		ERROR("System shutdown failed\n");
+	}
+
+	while (true) {
+		wfi();
+	}
+}
+
+/**
+ * versal2_validate_power_state() - Ensure that the power state
+ *                                  parameter in request is valid.
+ * @power_state: Power state of core.
+ * @req_state: Requested state.
+ *
+ * Return: Returns status, either PSCI_E_SUCCESS or reason.
+ */
+static int32_t versal2_validate_power_state(unsigned int power_state,
+					       psci_power_state_t *req_state)
+{
+	uint32_t pstate = psci_get_pstate_type(power_state);
+	int32_t ret = PSCI_E_SUCCESS;
+
+	VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
+
+	assert(req_state);
+
+	/* Sanity check the requested state */
+	if (pstate == PSTATE_TYPE_STANDBY) {
+		req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
+	} else {
+		req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
+	}
+
+	/* The 'state_id' is expected to be zero */
+	if (psci_get_pstate_id(power_state) != 0U) {
+		ret = PSCI_E_INVALID_PARAMS;
+	}
+
+	return ret;
+}
+
+/**
+ * versal2_get_sys_suspend_power_state() - Get power state for system
+ *                                            suspend.
+ * @req_state: Requested state.
+ */
+static void versal2_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+	uint64_t i;
+
+	for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
+		req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
+	}
+}
+
+/**
+ * Export the platform specific power ops.
+ */
+static const struct plat_psci_ops versal2_nopmc_psci_ops = {
+	.pwr_domain_on                  = versal2_pwr_domain_on,
+	.pwr_domain_off                 = versal2_pwr_domain_off,
+	.pwr_domain_on_finish           = versal2_pwr_domain_on_finish,
+	.pwr_domain_suspend             = versal2_pwr_domain_suspend,
+	.pwr_domain_suspend_finish      = versal2_pwr_domain_suspend_finish,
+	.system_off                     = versal2_system_off,
+	.system_reset                   = versal2_system_reset,
+	.validate_power_state           = versal2_validate_power_state,
+	.get_sys_suspend_power_state    = versal2_get_sys_suspend_power_state,
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+			    const struct plat_psci_ops **psci_ops)
+{
+	sec_entry = sec_entrypoint;
+
+	VERBOSE("Setting up entry point %lx\n", sec_entry);
+
+	*psci_ops = &versal2_nopmc_psci_ops;
+
+	return 0;
+}
+
+int32_t sip_svc_setup_init(void)
+{
+	return pm_setup();
+}
+
+uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+		     const void *cookie, void *handle, uint64_t flags)
+{
+	return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+}

plat/amd/versal2/platform.mk

@@ -28,6 +28,9 @@ PL011_GENERIC_UART := 1
 IPI_CRC_CHECK := 0
 GIC_ENABLE_V4_EXTN :=  0
 GICV3_SUPPORT_GIC600 := 1
+TFA_NO_PM := 1
+CPU_PWRDWN_SGI ?= 6
+$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI}))
 
 override CTX_INCLUDE_AARCH32_REGS    := 0
 
@@ -35,6 +38,10 @@ override CTX_INCLUDE_AARCH32_REGS    := 0
 override PLAT_XLAT_TABLES_DYNAMIC := 1
 $(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
 
+ifdef TFA_NO_PM
+   $(eval $(call add_define,TFA_NO_PM))
+endif
+
 ifdef MEM_BASE
     $(eval $(call add_define,MEM_BASE))
 
@@ -129,8 +136,17 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				drivers/scmi-msg/reset_domain.c			\
 				${PLAT_PATH}/scmi.c
 
-BL31_SOURCES		+=	${PLAT_PATH}/plat_psci.c			\
+ifeq ($(TFA_NO_PM), 0)
-				common/fdt_wrappers.c                           \
+BL31_SOURCES		+=	plat/xilinx/common/pm_service/pm_api_sys.c	\
+				plat/xilinx/common/pm_service/pm_ipi.c		\
+				${PLAT_PATH}/plat_psci_pm.c			\
+				plat/xilinx/common/pm_service/pm_svc_main.c	\
+				${PLAT_PATH}/pm_service/pm_client.c
+else
+BL31_SOURCES		+=	${PLAT_PATH}/plat_psci.c
+endif
+
+BL31_SOURCES		+=	common/fdt_wrappers.c                           \
 				plat/xilinx/common/plat_console.c               \
 				plat/xilinx/common/plat_startup.c		\
 				plat/xilinx/common/ipi.c			\

plat/amd/versal2/pm_service/pm_client.c

@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * APU specific definition of processors in the subsystem as well as functions
+ * for getting information about and changing state of the APU.
+ */
+
+#include <assert.h>
+
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv3.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+#include <lib/utils.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+#include "def.h"
+#include <plat_ipi.h>
+#include "pm_api_sys.h"
+#include "pm_client.h"
+
+#define UNDEFINED_CPUID	UINT32_MAX
+
+DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7)
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. Therefore, there is no doubt to use the spin_lock here.
+ */
+static spinlock_t pm_client_secure_lock;
+static inline void pm_client_lock_get(void)
+{
+	spin_lock(&pm_client_secure_lock);
+}
+
+static inline void pm_client_lock_release(void)
+{
+	spin_unlock(&pm_client_secure_lock);
+}
+
+static const struct pm_ipi apu_ipi = {
+	.local_ipi_id = IPI_LOCAL_ID,
+	.remote_ipi_id = IPI_REMOTE_ID,
+	.buffer_base = IPI_BUFFER_LOCAL_BASE,
+};
+
+/* Order in pm_procs_all array must match cpu ids */
+static const struct pm_proc pm_procs_all[] = {
+	{
+		.node_id = PM_DEV_CLUSTER0_ACPU_0,
+		.ipi = &apu_ipi,
+	},
+	{
+		.node_id = PM_DEV_CLUSTER0_ACPU_1,
+		.ipi = &apu_ipi,
+	},
+	{
+		.node_id = PM_DEV_CLUSTER1_ACPU_0,
+		.ipi = &apu_ipi,
+	},
+	{
+		.node_id = PM_DEV_CLUSTER1_ACPU_1,
+		.ipi = &apu_ipi,
+	},
+	{
+		.node_id = PM_DEV_CLUSTER2_ACPU_0,
+		.ipi = &apu_ipi,
+	},
+	{
+		.node_id = PM_DEV_CLUSTER2_ACPU_1,
+		.ipi = &apu_ipi,
+	},
+	{
+		.node_id = PM_DEV_CLUSTER3_ACPU_0,
+		.ipi = &apu_ipi,
+	},
+	{
+		.node_id = PM_DEV_CLUSTER3_ACPU_1,
+		.ipi = &apu_ipi,
+	},
+};
+
+const struct pm_proc *primary_proc = &pm_procs_all[0];
+
+/**
+ * pm_get_proc() - returns pointer to the proc structure.
+ * @cpuid: id of the cpu whose proc struct pointer should be returned.
+ *
+ * Return: Pointer to a proc structure if proc is found, otherwise NULL.
+ */
+const struct pm_proc *pm_get_proc(uint32_t cpuid)
+{
+	const struct pm_proc *proc = NULL;
+
+	if (cpuid < ARRAY_SIZE(pm_procs_all)) {
+		proc = &pm_procs_all[cpuid];
+	} else {
+		ERROR("cpuid: %d proc NULL\n", cpuid);
+	}
+
+	return proc;
+}
+
+/**
+ * irq_to_pm_node_idx - Get PM node index corresponding to the interrupt number.
+ * @irq: Interrupt number.
+ *
+ * Return: PM node index corresponding to the specified interrupt.
+ */
+enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq)
+{
+	enum pm_device_node_idx dev_idx = XPM_NODEIDX_DEV_MIN;
+
+	assert(irq <= IRQ_MAX);
+
+	switch (irq) {
+	case 11:
+		dev_idx = XPM_NODEIDX_DEV_I2C_2;
+		break;
+	case 12:
+		dev_idx = XPM_NODEIDX_DEV_I2C_3;
+		break;
+	case 13:
+		dev_idx = XPM_NODEIDX_DEV_I2C_4;
+		break;
+	case 20:
+		dev_idx = XPM_NODEIDX_DEV_GPIO;
+		break;
+	case 21:
+		dev_idx = XPM_NODEIDX_DEV_I2C_0;
+		break;
+	case 22:
+		dev_idx = XPM_NODEIDX_DEV_I2C_1;
+		break;
+	case 23:
+		dev_idx = XPM_NODEIDX_DEV_SPI_0;
+		break;
+	case 24:
+		dev_idx = XPM_NODEIDX_DEV_SPI_1;
+		break;
+	case 25:
+		dev_idx = XPM_NODEIDX_DEV_UART_0;
+		break;
+	case 26:
+		dev_idx = XPM_NODEIDX_DEV_UART_1;
+		break;
+	case 27:
+		dev_idx = XPM_NODEIDX_DEV_CAN_FD_0;
+		break;
+	case 28:
+		dev_idx = XPM_NODEIDX_DEV_CAN_FD_1;
+		break;
+	case 29:
+	case 30:
+	case 31:
+	case 32:
+	case 33:
+	case 98:
+		dev_idx = XPM_NODEIDX_DEV_USB_0;
+		break;
+	case 34:
+	case 35:
+	case 36:
+	case 37:
+	case 38:
+	case 99:
+		dev_idx = XPM_NODEIDX_DEV_USB_1;
+		break;
+	case 39:
+	case 40:
+		dev_idx = XPM_NODEIDX_DEV_GEM_0;
+		break;
+	case 41:
+	case 42:
+		dev_idx = XPM_NODEIDX_DEV_GEM_1;
+		break;
+	case 43:
+		dev_idx = XPM_NODEIDX_DEV_TTC_0;
+		break;
+	case 44:
+		dev_idx = XPM_NODEIDX_DEV_TTC_1;
+		break;
+	case 45:
+		dev_idx = XPM_NODEIDX_DEV_TTC_2;
+		break;
+	case 46:
+		dev_idx = XPM_NODEIDX_DEV_TTC_3;
+		break;
+	case 47:
+		dev_idx = XPM_NODEIDX_DEV_TTC_4;
+		break;
+	case 48:
+		dev_idx = XPM_NODEIDX_DEV_TTC_5;
+		break;
+	case 49:
+		dev_idx = XPM_NODEIDX_DEV_TTC_6;
+		break;
+	case 50:
+		dev_idx = XPM_NODEIDX_DEV_TTC_7;
+		break;
+	case 72:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_0;
+		break;
+	case 73:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_1;
+		break;
+	case 74:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_2;
+		break;
+	case 75:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_3;
+		break;
+	case 76:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_4;
+		break;
+	case 77:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_5;
+		break;
+	case 78:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_6;
+		break;
+	case 79:
+		dev_idx = XPM_NODEIDX_DEV_ADMA_7;
+		break;
+	case 95:
+		dev_idx = XPM_NODEIDX_DEV_CAN_FD_2;
+		break;
+	case 96:
+		dev_idx = XPM_NODEIDX_DEV_CAN_FD_3;
+		break;
+	case 100:
+		dev_idx = XPM_NODEIDX_DEV_I2C_5;
+		break;
+	case 101:
+		dev_idx = XPM_NODEIDX_DEV_I2C_6;
+		break;
+	case 102:
+		dev_idx = XPM_NODEIDX_DEV_I2C_7;
+		break;
+	case 200:
+		dev_idx = XPM_NODEIDX_DEV_RTC;
+		break;
+	case 218:
+		dev_idx = XPM_NODEIDX_DEV_SDIO_0;
+		break;
+	case 220:
+		dev_idx = XPM_NODEIDX_DEV_SDIO_1;
+		break;
+	default:
+		dev_idx = XPM_NODEIDX_DEV_MIN;
+		break;
+	}
+
+	return dev_idx;
+}
+
+/**
+ * pm_client_suspend() - Client-specific suspend actions. This function
+ *                       perform actions required prior to sending suspend
+ *                       request.
+ *                       Actions taken depend on the state system is
+ *                       suspending to.
+ * @proc: processor which need to suspend.
+ * @state: desired suspend state.
+ */
+void pm_client_suspend(const struct pm_proc *proc, uint32_t state)
+{
+	uint32_t cpu_id = plat_my_core_pos();
+	uintptr_t val;
+	/*
+	 * Get the core index, use it calculate offset for secondary cores
+	 * to match with register database
+	 */
+	uint32_t core_index = cpu_id + ((cpu_id / 2U) * 2U);
+
+	pm_client_lock_get();
+
+	if (state == PM_STATE_SUSPEND_TO_RAM) {
+		pm_client_set_wakeup_sources((uint32_t)proc->node_id);
+	}
+
+	val = read_cpu_pwrctrl_val();
+	val |= CORE_PWRDN_EN_BIT_MASK;
+	write_cpu_pwrctrl_val(val);
+
+	isb();
+
+	/* Enable power down interrupt */
+	mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(core_index),
+		      APU_PCIL_CORE_X_IEN_POWER_MASK);
+	/* Enable wake interrupt */
+	mmio_write_32(APU_PCIL_CORE_X_IEN_WAKE_REG(core_index),
+		      APU_PCIL_CORE_X_IEN_WAKE_MASK);
+
+	pm_client_lock_release();
+}
+
+/**
+ * pm_get_cpuid() - get the local cpu ID for a global node ID.
+ * @nid: node id of the processor.
+ *
+ * Return: the cpu ID (starting from 0) for the subsystem.
+ */
+static uint32_t pm_get_cpuid(uint32_t nid)
+{
+	uint32_t ret = (uint32_t) UNDEFINED_CPUID;
+	size_t i;
+
+	for (i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
+		if (pm_procs_all[i].node_id == nid) {
+			ret = (uint32_t)i;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * pm_client_wakeup() - Client-specific wakeup actions.
+ * @proc: Processor which need to wakeup.
+ *
+ * This function should contain any PU-specific actions
+ * required for waking up another APU core.
+ */
+void pm_client_wakeup(const struct pm_proc *proc)
+{
+	uint32_t cpuid = pm_get_cpuid(proc->node_id);
+	uintptr_t val;
+
+	if (cpuid != (uint32_t) UNDEFINED_CPUID) {
+		pm_client_lock_get();
+
+		/* Clear powerdown request */
+		val = read_cpu_pwrctrl_val();
+		val &= ~CORE_PWRDN_EN_BIT_MASK;
+		write_cpu_pwrctrl_val(val);
+
+		isb();
+
+		/* Disabled power down interrupt */
+		mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
+			      APU_PCIL_CORE_X_IDS_POWER_MASK);
+		/* Disable wake interrupt */
+		mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
+			      APU_PCIL_CORE_X_IDS_WAKE_MASK);
+
+		pm_client_lock_release();
+	}
+}
+
+/**
+ * pm_client_abort_suspend() - Client-specific abort-suspend actions.
+ *
+ * This function should contain any PU-specific actions
+ * required for aborting a prior suspend request.
+ */
+void pm_client_abort_suspend(void)
+{
+	uint32_t cpu_id = plat_my_core_pos();
+	uintptr_t val;
+
+	/* Enable interrupts at processor level (for current cpu) */
+	gicv3_cpuif_enable(plat_my_core_pos());
+
+	pm_client_lock_get();
+
+	/* Clear powerdown request */
+	val = read_cpu_pwrctrl_val();
+	val &= ~CORE_PWRDN_EN_BIT_MASK;
+	write_cpu_pwrctrl_val(val);
+
+	isb();
+
+	/* Disabled power down interrupt */
+	mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id),
+		      APU_PCIL_CORE_X_IDS_POWER_MASK);
+
+	pm_client_lock_release();
+}

plat/xilinx/common/include/pm_node.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -132,6 +132,18 @@ enum pm_device_node_idx {
 	XPM_NODEIDX_DEV_TTC_2 = 0x26,
 	XPM_NODEIDX_DEV_TTC_3 = 0x27,
 	XPM_NODEIDX_DEV_SWDT_LPD = 0x28,
+	XPM_NODEIDX_DEV_I2C_2 = 0x117,
+	XPM_NODEIDX_DEV_I2C_3 = 0x118,
+	XPM_NODEIDX_DEV_I2C_4 = 0x119,
+	XPM_NODEIDX_DEV_I2C_5 = 0x11A,
+	XPM_NODEIDX_DEV_I2C_6 = 0x11B,
+	XPM_NODEIDX_DEV_I2C_7 = 0x11C,
+	XPM_NODEIDX_DEV_CAN_FD_2 = 0x11D,
+	XPM_NODEIDX_DEV_CAN_FD_3 = 0x11E,
+	XPM_NODEIDX_DEV_TTC_4 = 0x11F,
+	XPM_NODEIDX_DEV_TTC_5 = 0x120,
+	XPM_NODEIDX_DEV_TTC_6 = 0x121,
+	XPM_NODEIDX_DEV_TTC_7 = 0x122,
 
 	/* FPD Peripheral devices */
 	XPM_NODEIDX_DEV_SWDT_FPD = 0x29,
@@ -237,6 +249,11 @@ enum pm_device_node_idx {
 	XPM_NODEIDX_DEV_FPD_SWDT_2 = 0xDD,
 	XPM_NODEIDX_DEV_FPD_SWDT_3 = 0xDE,
 #endif
+
+#if defined(PLAT_versal2)
+	XPM_NODEIDX_DEV_USB_1 = 0xD7,
+#endif
+
 	XPM_NODEIDX_DEV_MAX,
 };