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https://github.com/ARM-software/arm-trusted-firmware.git
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414cf08b76
Add support for PM functionality through EEMI interface for Versal Gen 2. Add support of PM APIs in PSCI ops. Add TFA_NO_PM flag to disable PM functionality. Enable wakeup for new peripherals Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2 Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
340 lines
8.5 KiB
C
340 lines
8.5 KiB
C
/*
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* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <plat_arm.h>
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#include "def.h"
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#include <ipi.h>
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#include <plat_private.h>
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#include "pm_api_sys.h"
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#include "pm_client.h"
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#include <pm_common.h>
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#include "pm_defs.h"
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#include "pm_svc_main.h"
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static uintptr_t sec_entry;
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static int32_t versal2_pwr_domain_on(u_register_t mpidr)
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{
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int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
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int32_t ret = (int32_t) PSCI_E_INTERN_FAIL;
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enum pm_ret_status pm_ret;
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const struct pm_proc *proc;
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if (cpu_id != -1) {
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proc = pm_get_proc((uint32_t)cpu_id);
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if (proc != NULL) {
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pm_ret = pm_req_wakeup(proc->node_id,
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(uint32_t)
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((sec_entry & 0xFFFFFFFFU) | 0x1U),
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sec_entry >> 32, 0, 0);
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if (pm_ret == PM_RET_SUCCESS) {
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/* Clear power down request */
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pm_client_wakeup(proc);
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ret = (int32_t) PSCI_E_SUCCESS;
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}
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}
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}
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return ret;
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}
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/**
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* versal2_pwr_domain_off() - Turn off core.
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* @target_state: Targeted state.
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*/
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static void versal2_pwr_domain_off(const psci_power_state_t *target_state)
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{
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const struct pm_proc *proc;
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uint32_t cpu_id = plat_my_core_pos();
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enum pm_ret_status pm_ret;
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size_t i;
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proc = pm_get_proc(cpu_id);
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if (proc == NULL) {
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ERROR("Failed to get proc %d\n", cpu_id);
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goto err;
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}
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for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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}
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plat_gic_cpuif_disable();
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/*
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* Send request to PMC to power down the appropriate APU CPU
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* core.
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* According to PSCI specification, CPU_off function does not
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* have resume address and CPU core can only be woken up
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* invoking CPU_on function, during which resume address will
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* be set.
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*/
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pm_ret = pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
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SECURE_FLAG);
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if (pm_ret != PM_RET_SUCCESS) {
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ERROR("Failed to power down CPU %d\n", cpu_id);
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}
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err:
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return;
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}
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/**
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* versal2_system_reset() - Send the reset request to firmware for the
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* system to reset. This function does not
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* return as it resets system.
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*/
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static void __dead2 versal2_system_reset(void)
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{
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uint32_t timeout = 10000U;
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enum pm_ret_status pm_ret;
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int32_t ret;
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request_cpu_pwrdwn();
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/*
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* Send the system reset request to the firmware if power down request
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* is not received from firmware.
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*/
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if (pwrdwn_req_received == true) {
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/*
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* TODO: shutdown scope for this reset needs be revised once
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* we have a clearer understanding of the overall reset scoping
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* including the implementation of SYSTEM_RESET2.
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*/
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pm_ret = pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
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pm_get_shutdown_scope(), SECURE_FLAG);
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if (pm_ret != PM_RET_SUCCESS) {
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WARN("System shutdown failed\n");
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}
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/*
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* Wait for system shutdown request completed and idle callback
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* not received.
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*/
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do {
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ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id,
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primary_proc->ipi->remote_ipi_id);
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udelay(100);
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timeout--;
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} while ((ret != (int32_t)IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U));
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}
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(void)psci_cpu_off();
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while (true) {
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wfi();
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}
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}
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/**
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* versal2_pwr_domain_suspend() - Send request to PMC to suspend core.
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* @target_state: Targeted state.
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*/
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static void versal2_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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const struct pm_proc *proc;
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uint32_t cpu_id = plat_my_core_pos();
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uint32_t state;
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enum pm_ret_status ret;
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size_t i;
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proc = pm_get_proc(cpu_id);
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if (proc == NULL) {
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ERROR("Failed to get proc %d\n", cpu_id);
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goto err;
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}
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for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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}
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plat_gic_cpuif_disable();
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if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
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plat_gic_save();
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}
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state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ?
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PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
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/* Send request to PMC to suspend this core */
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ret = pm_self_suspend(proc->node_id, MAX_LATENCY, state, sec_entry,
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SECURE_FLAG);
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if (ret != PM_RET_SUCCESS) {
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ERROR("Failed to power down CPU %d\n", cpu_id);
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}
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err:
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return;
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}
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static void versal2_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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(void)target_state;
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/* Enable the gic cpu interface */
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plat_gic_pcpu_init();
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/* Program the gic per-cpu distributor or re-distributor interface */
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plat_gic_cpuif_enable();
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}
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/**
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* versal2_pwr_domain_suspend_finish() - Performs actions to finish
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* suspend procedure.
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* @target_state: Targeted state.
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*/
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static void versal2_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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const struct pm_proc *proc;
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uint32_t cpu_id = plat_my_core_pos();
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size_t i;
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proc = pm_get_proc(cpu_id);
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if (proc == NULL) {
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ERROR("Failed to get proc %d\n", cpu_id);
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goto err;
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}
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for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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}
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/* Clear the APU power control register for this cpu */
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pm_client_wakeup(proc);
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/* APU was turned off, so restore GIC context */
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if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
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plat_gic_resume();
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}
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plat_gic_cpuif_enable();
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err:
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return;
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}
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/**
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* versal2_system_off() - Send the system off request to firmware.
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* This function does not return as it puts core into WFI
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*/
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static void __dead2 versal2_system_off(void)
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{
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enum pm_ret_status ret;
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/* Send the power down request to the PMC */
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ret = pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
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pm_get_shutdown_scope(), SECURE_FLAG);
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if (ret != PM_RET_SUCCESS) {
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ERROR("System shutdown failed\n");
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}
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while (true) {
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wfi();
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}
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}
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/**
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* versal2_validate_power_state() - Ensure that the power state
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* parameter in request is valid.
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* @power_state: Power state of core.
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* @req_state: Requested state.
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*
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* Return: Returns status, either PSCI_E_SUCCESS or reason.
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*/
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static int32_t versal2_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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uint32_t pstate = psci_get_pstate_type(power_state);
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int32_t ret = PSCI_E_SUCCESS;
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VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
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assert(req_state);
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/* Sanity check the requested state */
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if (pstate == PSTATE_TYPE_STANDBY) {
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
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} else {
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
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}
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/* The 'state_id' is expected to be zero */
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if (psci_get_pstate_id(power_state) != 0U) {
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ret = PSCI_E_INVALID_PARAMS;
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}
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return ret;
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}
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/**
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* versal2_get_sys_suspend_power_state() - Get power state for system
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* suspend.
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* @req_state: Requested state.
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*/
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static void versal2_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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uint64_t i;
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for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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}
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/**
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* Export the platform specific power ops.
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*/
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static const struct plat_psci_ops versal2_nopmc_psci_ops = {
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.pwr_domain_on = versal2_pwr_domain_on,
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.pwr_domain_off = versal2_pwr_domain_off,
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.pwr_domain_on_finish = versal2_pwr_domain_on_finish,
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.pwr_domain_suspend = versal2_pwr_domain_suspend,
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.pwr_domain_suspend_finish = versal2_pwr_domain_suspend_finish,
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.system_off = versal2_system_off,
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.system_reset = versal2_system_reset,
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.validate_power_state = versal2_validate_power_state,
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.get_sys_suspend_power_state = versal2_get_sys_suspend_power_state,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const struct plat_psci_ops **psci_ops)
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{
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sec_entry = sec_entrypoint;
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VERBOSE("Setting up entry point %lx\n", sec_entry);
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*psci_ops = &versal2_nopmc_psci_ops;
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return 0;
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}
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int32_t sip_svc_setup_init(void)
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{
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return pm_setup();
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}
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uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
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const void *cookie, void *handle, uint64_t flags)
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{
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return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
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}
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