mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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414cf08b76
Add support for PM functionality through EEMI interface for Versal Gen 2. Add support of PM APIs in PSCI ops. Add TFA_NO_PM flag to disable PM functionality. Enable wakeup for new peripherals Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2 Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
186 lines
5.2 KiB
Makefile
186 lines
5.2 KiB
Makefile
# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
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# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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PLAT_PATH := plat/amd/versal2
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override NEED_BL1 := no
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override NEED_BL2 := no
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# A78 Erratum for SoC
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ERRATA_A78_AE_1941500 := 1
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ERRATA_A78_AE_1951502 := 1
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ERRATA_A78_AE_2376748 := 1
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ERRATA_A78_AE_2395408 := 1
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ERRATA_ABI_SUPPORT := 1
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# Platform Supports Armv8.2 extensions
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ARM_ARCH_MAJOR := 8
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ARM_ARCH_MINOR := 2
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override PROGRAMMABLE_RESET_ADDRESS := 1
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PSCI_EXTENDED_STATE_ID := 1
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SEPARATE_CODE_AND_RODATA := 1
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override RESET_TO_BL31 := 1
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PL011_GENERIC_UART := 1
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IPI_CRC_CHECK := 0
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GIC_ENABLE_V4_EXTN := 0
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GICV3_SUPPORT_GIC600 := 1
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TFA_NO_PM := 1
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CPU_PWRDWN_SGI ?= 6
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$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI}))
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override CTX_INCLUDE_AARCH32_REGS := 0
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# Platform to support Dynamic XLAT Table by default
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override PLAT_XLAT_TABLES_DYNAMIC := 1
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$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
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ifdef TFA_NO_PM
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$(eval $(call add_define,TFA_NO_PM))
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endif
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ifdef MEM_BASE
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$(eval $(call add_define,MEM_BASE))
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ifndef MEM_SIZE
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$(error "MEM_BASE defined without MEM_SIZE")
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endif
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$(eval $(call add_define,MEM_SIZE))
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ifdef MEM_PROGBITS_SIZE
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$(eval $(call add_define,MEM_PROGBITS_SIZE))
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endif
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endif
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ifdef BL32_MEM_BASE
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$(eval $(call add_define,BL32_MEM_BASE))
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ifndef BL32_MEM_SIZE
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$(error "BL32_MEM_BASE defined without BL32_MEM_SIZE")
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endif
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$(eval $(call add_define,BL32_MEM_SIZE))
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endif
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ifdef IPI_CRC_CHECK
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$(eval $(call add_define,IPI_CRC_CHECK))
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endif
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USE_COHERENT_MEM := 0
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HW_ASSISTED_COHERENCY := 1
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VERSAL2_CONSOLE ?= pl011
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ifeq (${VERSAL2_CONSOLE}, $(filter ${VERSAL2_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none))
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else
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$(error "Please define VERSAL2_CONSOLE")
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endif
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$(eval $(call add_define_val,VERSAL2_CONSOLE,VERSAL2_CONSOLE_ID_${VERSAL2_CONSOLE}))
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# Runtime console in default console in DEBUG build
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ifeq ($(DEBUG), 1)
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CONSOLE_RUNTIME ?= pl011
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endif
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# Runtime console
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ifdef CONSOLE_RUNTIME
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ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb))
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$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
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else
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$(error "Please define CONSOLE_RUNTIME")
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endif
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endif
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ifeq (${TRANSFER_LIST},0)
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XILINX_OF_BOARD_DTB_ADDR ?= 0x1000000
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$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
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endif
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iplat/xilinx/common/include/ \
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-Iplat/amd/common/include/ \
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-Iplat/xilinx/common/ipi_mailbox_service/ \
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-I${PLAT_PATH}/include/ \
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-Iplat/xilinx/versal/pm_service/
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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include lib/libfdt/libfdt.mk
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PLAT_BL_COMMON_SOURCES := \
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drivers/arm/dcc/dcc_console.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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${GICV3_SOURCES} \
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drivers/arm/pl011/aarch64/pl011_console.S \
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plat/common/aarch64/crash_console_helpers.S \
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plat/arm/common/arm_common.c \
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plat/common/plat_gicv3.c \
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${PLAT_PATH}/aarch64/helpers.S \
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${PLAT_PATH}/aarch64/common.c \
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${PLAT_PATH}/plat_topology.c \
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${XLAT_TABLES_LIB_SRCS}
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BL31_SOURCES += drivers/arm/cci/cci.c \
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lib/cpus/aarch64/cortex_a78_ae.S \
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lib/cpus/aarch64/cortex_a78.S \
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plat/common/plat_psci_common.c \
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drivers/scmi-msg/base.c \
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drivers/scmi-msg/entry.c \
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drivers/scmi-msg/smt.c \
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drivers/scmi-msg/clock.c \
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drivers/scmi-msg/power_domain.c \
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drivers/scmi-msg/reset_domain.c \
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${PLAT_PATH}/scmi.c
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ifeq ($(TFA_NO_PM), 0)
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BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \
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plat/xilinx/common/pm_service/pm_ipi.c \
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${PLAT_PATH}/plat_psci_pm.c \
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plat/xilinx/common/pm_service/pm_svc_main.c \
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${PLAT_PATH}/pm_service/pm_client.c
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else
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BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
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endif
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BL31_SOURCES += common/fdt_wrappers.c \
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plat/xilinx/common/plat_console.c \
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plat/xilinx/common/plat_startup.c \
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plat/xilinx/common/ipi.c \
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plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
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${PLAT_PATH}/soc_ipi.c \
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plat/xilinx/common/versal.c \
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${PLAT_PATH}/bl31_setup.c \
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common/fdt_fixup.c \
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common/fdt_wrappers.c \
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${LIBFDT_SRCS} \
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${PLAT_PATH}/sip_svc_setup.c \
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${PLAT_PATH}/gicv3.c
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ifeq (${ERRATA_ABI_SUPPORT}, 1)
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# enable the cpu macros for errata abi interface
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CORTEX_A78_AE_H_INC := 1
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$(eval $(call add_define, CORTEX_A78_AE_H_INC))
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endif
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# Enable Handoff protocol using transfer lists
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TRANSFER_LIST ?= 0
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ifeq (${TRANSFER_LIST},1)
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include lib/transfer_list/transfer_list.mk
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BL31_SOURCES += plat/amd/common/plat_fdt.c
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BL31_SOURCES += plat/amd/common/plat_xfer_list.c
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else
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BL31_SOURCES += plat/xilinx/common/plat_fdt.c
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endif
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XLNX_DT_CFG ?= 1
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ifeq (${TRANSFER_LIST},0)
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ifndef XILINX_OF_BOARD_DTB_ADDR
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XLNX_DT_CFG := 0
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endif
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endif
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$(eval $(call add_define,XLNX_DT_CFG))
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