mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
Merge "refactor(tegra132): deprecate platform" into integration
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
391828923f
9 changed files with 15 additions and 748 deletions
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@ -19,7 +19,7 @@ The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous
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multi-processing (HMP) solution designed to optimize performance and
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efficiency.
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T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
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T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
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in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
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support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
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including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
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@ -29,20 +29,6 @@ Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
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high speed coherency fabric connects these two processor complexes and allows
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heterogeneous multi-processing with all six cores if required.
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- .. rubric:: T210
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:name: t210
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T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
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companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
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support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
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including legacy Armv7-A applications. The Cortex-A57 processors each have
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48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
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Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
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and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
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- .. rubric:: T132
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:name: t132
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Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
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fully Armv8-A architecture compatible. Each of the two Denver cores
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implements a 7-way superscalar microarchitecture (up to 7 concurrent
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@ -68,6 +54,17 @@ Denver also features new low latency power-state transitions, in addition
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to extensive power-gating and dynamic voltage and clock scaling based on
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workloads.
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- .. rubric:: T210
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:name: t210
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T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
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companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
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support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
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including legacy Armv7-A applications. The Cortex-A57 processors each have
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48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
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Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
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and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
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Directory structure
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-------------------
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@ -89,7 +86,6 @@ their dispatchers in the image without changing any makefiles.
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These are the supported Trusted OS' by Tegra platforms.
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- Tegra132: TLK
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- Tegra210: TLK and Trusty
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- Tegra186: Trusty
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- Tegra194: Trusty
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@ -110,7 +106,7 @@ Preparing the BL31 image to run on Tegra SoCs
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.. code:: shell
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CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
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TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
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TARGET_SOC=<target-soc e.g. t194|t186|t210> SPD=<dispatcher e.g. trusty|tlkd>
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bl31
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Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -82,13 +82,6 @@ static uint32_t tegra_get_chipid_pre_si_platform(void)
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return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK;
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}
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bool tegra_chipid_is_t132(void)
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{
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uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
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return (chip_id == TEGRA_CHIPID_TEGRA13);
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}
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bool tegra_chipid_is_t186(void)
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{
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uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
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@ -1,127 +0,0 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TEGRA_DEF_H
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#define TEGRA_DEF_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Platform BL31 specific defines.
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******************************************************************************/
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#define BL31_SIZE U(0x40000)
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/*******************************************************************************
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* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call as the `state-id` field in the 'power state' parameter.
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******************************************************************************/
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#define PSTATE_ID_SOC_POWERDN U(0xD)
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/*******************************************************************************
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* Platform power states (used by PSCI framework)
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*
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* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
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* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
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******************************************************************************/
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
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/*******************************************************************************
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* Chip specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
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/*******************************************************************************
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* GIC memory map
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******************************************************************************/
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#define TEGRA_GICD_BASE U(0x50041000)
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#define TEGRA_GICC_BASE U(0x50042000)
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE U(0x60005010)
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#define TEGRA_TMRUS_SIZE U(0x1000)
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE U(0x60006000)
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#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
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#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
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#define GPU_RESET_BIT (U(1) << 24)
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#define GPU_SET_BIT (U(1) << 24)
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/*******************************************************************************
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* Tegra Flow Controller constants
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******************************************************************************/
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#define TEGRA_FLOWCTRL_BASE U(0x60007000)
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/*******************************************************************************
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* Tegra Secure Boot Controller constants
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******************************************************************************/
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#define TEGRA_SB_BASE U(0x6000C200)
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/*******************************************************************************
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* Tegra Exception Vectors constants
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******************************************************************************/
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#define TEGRA_EVP_BASE U(0x6000F000)
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/*******************************************************************************
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* Tegra Miscellaneous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE U(0x70000000)
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#define HARDWARE_REVISION_OFFSET U(0x804)
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/*******************************************************************************
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* Tegra UART controller base addresses
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******************************************************************************/
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#define TEGRA_UARTA_BASE U(0x70006000)
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#define TEGRA_UARTB_BASE U(0x70006040)
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#define TEGRA_UARTC_BASE U(0x70006200)
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#define TEGRA_UARTD_BASE U(0x70006300)
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#define TEGRA_UARTE_BASE U(0x70006400)
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE U(0x7000E400)
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_BASE U(0x70019000)
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/* Memory Controller Interrupt Status */
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#define MC_INTSTATUS 0x00U
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 U(0x70)
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#define MC_SECURITY_CFG1_0 U(0x74)
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#define MC_SECURITY_CFG3_0 U(0x9BC)
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
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#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
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#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
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#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
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#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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#define TEGRA_TZRAM_BASE U(0x7C010000)
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#define TEGRA_TZRAM_SIZE U(0x10000)
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/*******************************************************************************
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* Tegra DRAM memory base address
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******************************************************************************/
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#define TEGRA_DRAM_BASE ULL(0x80000000)
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#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
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#endif /* TEGRA_DEF_H */
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -49,7 +49,6 @@ uint32_t tegra_get_chipid_minor(void);
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/*
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* Tegra chip ID identifiers
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*/
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bool tegra_chipid_is_t132(void);
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bool tegra_chipid_is_t186(void);
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bool tegra_chipid_is_t210(void);
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bool tegra_chipid_is_t210_b01(void);
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@ -1,208 +0,0 @@
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <denver.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <flowctrl.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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/*
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* Register used to clear CPU reset signals. Each CPU has two reset
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* signals: CPU reset (3:0) and Core reset (19:16)
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*/
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#define CPU_CMPLX_RESET_CLR 0x344
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#define CPU_CORE_RESET_MASK 0x10001
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/* Clock and Reset controller registers for system clock's settings */
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#define SCLK_RATE 0x30
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#define SCLK_BURST_POLICY 0x28
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#define SCLK_BURST_POLICY_DEFAULT 0x10000000
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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const plat_local_state_t *states,
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uint32_t ncpu)
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{
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plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
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uint32_t num_cpu = ncpu;
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const plat_local_state_t *local_state = states;
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(void)lvl;
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assert(ncpu != 0U);
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do {
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temp = *local_state;
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if ((temp < target)) {
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target = temp;
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}
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--num_cpu;
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local_state++;
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} while (num_cpu != 0U);
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return target;
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}
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int32_t tegra_soc_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int state_id = psci_get_pstate_id(power_state);
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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/*
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* Sanity check the requested state id, power level and CPU number.
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* Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
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* i.e. CPU 0
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*/
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if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) {
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ERROR("unsupported state id @ power level\n");
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return PSCI_E_INVALID_PARAMS;
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}
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/* Set lower power states to PLAT_MAX_OFF_STATE */
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for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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/* Set the SYSTEM_SUSPEND state-id */
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
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PSTATE_ID_SOC_POWERDN;
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t mask = CPU_CORE_RESET_MASK << cpu;
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if (cpu_powergate_mask[cpu] == 0) {
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/* Deassert CPU reset signals */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
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/* Power on CPU using PMC */
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tegra_pmc_cpu_on(cpu);
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/* Fill in the CPU powergate mask */
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cpu_powergate_mask[cpu] = 1;
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} else {
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/* Power on CPU using Flow Controller */
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tegra_fc_cpu_on(cpu);
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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/*
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* Lock scratch registers which hold the CPU vectors
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*/
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tegra_pmc_lock_cpu_vectors();
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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uint64_t val;
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tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
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/* Disable DCO operations */
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denver_disable_dco();
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/* Power down the CPU */
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val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
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write_actlr_el1(val | DENVER_CPU_STATE_POWER_DOWN);
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
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{
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(void)cpu_state;
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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uint64_t val;
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#if ENABLE_ASSERTIONS
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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/* SYSTEM_SUSPEND only on CPU0 */
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assert(cpu == 0);
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#endif
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/* Allow restarting CPU #1 using PMC on suspend exit */
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cpu_powergate_mask[1] = 0;
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/* Program FC to enter suspend state */
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tegra_fc_cpu_powerdn(read_mpidr());
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/* Disable DCO operations */
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denver_disable_dco();
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/* Program the suspend state ID */
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val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
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write_actlr_el1(val | target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_system_reset(void)
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{
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/*
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* Set System Clock (SCLK) to POR default so that the clock source
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* for the PMC APB clock would not be changed due to system reset.
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*/
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mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
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SCLK_BURST_POLICY_DEFAULT);
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mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
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/* Wait 1 ms to make sure clock source/device logic is stabilized. */
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mdelay(1);
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/*
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* Program the PMC in order to restart the system.
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*/
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tegra_pmc_system_reset();
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||||
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return PSCI_E_SUCCESS;
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||||
}
|
||||
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||||
__dead2 void tegra_soc_prepare_system_off(void)
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||||
{
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||||
ERROR("Tegra System Off: operation not handled.\n");
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panic();
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}
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|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <denver.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <pmc.h>
|
||||
#include <tegra_def.h>
|
||||
|
||||
#define SB_CSR 0x0
|
||||
#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
|
||||
|
||||
/* AARCH64 CPU reset vector */
|
||||
#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */
|
||||
#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */
|
||||
|
||||
/* AARCH32 CPU reset vector */
|
||||
#define EVP_CPU_RESET_VECTOR 0x100
|
||||
|
||||
extern void tegra_secure_entrypoint(void);
|
||||
|
||||
/*
|
||||
* For T132, CPUs reset to AARCH32, so the reset vector is first
|
||||
* armv8_trampoline which does a warm reset to AARCH64 and starts
|
||||
* execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI.
|
||||
*/
|
||||
__aligned(8) const uint32_t armv8_trampoline[] = {
|
||||
0xE3A00003, /* mov r0, #3 */
|
||||
0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */
|
||||
0xEAFFFFFE, /* b . */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Setup secondary CPU vectors
|
||||
******************************************************************************/
|
||||
void plat_secondary_setup(void)
|
||||
{
|
||||
uint32_t val;
|
||||
uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint;
|
||||
|
||||
/*
|
||||
* For T132, CPUs reset to AARCH32, so the reset vector is first
|
||||
* armv8_trampoline, which does a warm reset to AARCH64 and starts
|
||||
* execution at the address in SCRATCH34/SCRATCH35.
|
||||
*/
|
||||
INFO("Setting up T132 CPU boot\n");
|
||||
|
||||
/* initial AARCH32 reset address */
|
||||
tegra_pmc_write_32(PMC_SECURE_SCRATCH22,
|
||||
(unsigned long)&armv8_trampoline);
|
||||
|
||||
/* set AARCH32 exception vector (read to flush) */
|
||||
mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR,
|
||||
(unsigned long)&armv8_trampoline);
|
||||
val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR);
|
||||
|
||||
/* setup secondary CPU vector */
|
||||
mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
|
||||
(reset_addr & 0xFFFFFFFF) | 1);
|
||||
val = reset_addr >> 32;
|
||||
mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
|
||||
|
||||
/* configure PMC */
|
||||
tegra_pmc_cpu_setup(reset_addr);
|
||||
tegra_pmc_lock_cpu_vectors();
|
||||
}
|
||||
|
|
@ -1,201 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <drivers/console.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <memctrl.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <tegra_def.h>
|
||||
#include <tegra_platform.h>
|
||||
#include <tegra_private.h>
|
||||
|
||||
/* sets of MMIO ranges setup */
|
||||
#define MMIO_RANGE_0_ADDR 0x50000000
|
||||
#define MMIO_RANGE_1_ADDR 0x60000000
|
||||
#define MMIO_RANGE_2_ADDR 0x70000000
|
||||
#define MMIO_RANGE_SIZE 0x200000
|
||||
|
||||
/*
|
||||
* Table of regions to map using the MMU.
|
||||
*/
|
||||
static const mmap_region_t tegra_mmap[] = {
|
||||
MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
{0}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Set up the pagetables as per the platform memory map & initialize the MMU
|
||||
******************************************************************************/
|
||||
const mmap_region_t *plat_get_mmio_map(void)
|
||||
{
|
||||
/* MMIO space */
|
||||
return tegra_mmap;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* The Tegra power domain tree has a single system level power domain i.e. a
|
||||
* single root node. The first entry in the power domain descriptor specifies
|
||||
* the number of power domains at the highest power level.
|
||||
*******************************************************************************
|
||||
*/
|
||||
const unsigned char tegra_power_domain_tree_desc[] = {
|
||||
/* No of root nodes */
|
||||
1,
|
||||
/* No of clusters */
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
/* No of CPU cores */
|
||||
PLATFORM_CORE_COUNT,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the Tegra default topology tree information.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return tegra_power_domain_tree_desc;
|
||||
}
|
||||
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
return 12000000;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Maximum supported UART controllers
|
||||
******************************************************************************/
|
||||
#define TEGRA132_MAX_UART_PORTS 5
|
||||
|
||||
/*******************************************************************************
|
||||
* This variable holds the UART port base addresses
|
||||
******************************************************************************/
|
||||
static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
|
||||
0, /* undefined - treated as an error case */
|
||||
TEGRA_UARTA_BASE,
|
||||
TEGRA_UARTB_BASE,
|
||||
TEGRA_UARTC_BASE,
|
||||
TEGRA_UARTD_BASE,
|
||||
TEGRA_UARTE_BASE,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Enable console corresponding to the console ID
|
||||
******************************************************************************/
|
||||
void plat_enable_console(int32_t id)
|
||||
{
|
||||
static console_t uart_console;
|
||||
uint32_t console_clock;
|
||||
|
||||
if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
|
||||
/*
|
||||
* Reference clock used by the FPGAs is a lot slower.
|
||||
*/
|
||||
if (tegra_platform_is_fpga()) {
|
||||
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
|
||||
} else {
|
||||
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
|
||||
}
|
||||
|
||||
(void)console_16550_register(tegra132_uart_addresses[id],
|
||||
console_clock,
|
||||
TEGRA_CONSOLE_BAUDRATE,
|
||||
&uart_console);
|
||||
console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
|
||||
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the GIC and SGIs
|
||||
******************************************************************************/
|
||||
void plat_gic_setup(void)
|
||||
{
|
||||
tegra_gic_setup(NULL, 0);
|
||||
tegra_gic_init();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Return pointer to the BL31 params from previous bootloader
|
||||
******************************************************************************/
|
||||
struct tegra_bl31_params *plat_get_bl31_params(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Return pointer to the BL31 platform params from previous bootloader
|
||||
******************************************************************************/
|
||||
plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler for early platform setup
|
||||
******************************************************************************/
|
||||
void plat_early_platform_setup(void)
|
||||
{
|
||||
plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
|
||||
|
||||
/* Verify chip id is t132 */
|
||||
assert(tegra_chipid_is_t132());
|
||||
|
||||
/*
|
||||
* Do initial security configuration to allow DRAM/device access.
|
||||
*/
|
||||
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
|
||||
(uint32_t)plat_params->tzdram_size);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler for late platform setup
|
||||
******************************************************************************/
|
||||
void plat_late_platform_setup(void)
|
||||
{
|
||||
; /* do nothing */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler to indicate support for System Suspend
|
||||
******************************************************************************/
|
||||
bool plat_supports_system_suspend(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific runtime setup.
|
||||
******************************************************************************/
|
||||
void plat_runtime_setup(void)
|
||||
{
|
||||
/*
|
||||
* During cold boot, it is observed that the arbitration
|
||||
* bit is set in the Memory controller leading to false
|
||||
* error interrupts in the non-secure world. To avoid
|
||||
* this, clean the interrupt status register before
|
||||
* booting into the non-secure world
|
||||
*/
|
||||
tegra_memctrl_clear_pending_interrupts();
|
||||
|
||||
/*
|
||||
* During boot, USB3 and flash media (SDMMC/SATA) devices need
|
||||
* access to IRAM. Because these clients connect to the MC and
|
||||
* do not have a direct path to the IRAM, the MC implements AHB
|
||||
* redirection during boot to allow path to IRAM. In this mode
|
||||
* accesses to a programmed memory address aperture are directed
|
||||
* to the AHB bus, allowing access to the IRAM. This mode must be
|
||||
* disabled before we jump to the non-secure world.
|
||||
*/
|
||||
tegra_memctrl_disable_ahb_redirection();
|
||||
}
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <lib/el3_runtime/context_mgmt.h>
|
||||
|
||||
#include <tegra_private.h>
|
||||
|
||||
#define NS_SWITCH_AARCH32 1
|
||||
#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra132 SiP SMCs
|
||||
******************************************************************************/
|
||||
#define TEGRA_SIP_AARCH_SWITCH 0x82000004
|
||||
|
||||
/*******************************************************************************
|
||||
* SPSR settings for AARCH32/AARCH64 modes
|
||||
******************************************************************************/
|
||||
#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \
|
||||
DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)
|
||||
#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
|
||||
|
||||
/*******************************************************************************
|
||||
* This function is responsible for handling all T132 SiP calls
|
||||
******************************************************************************/
|
||||
int plat_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
uint64_t x3,
|
||||
uint64_t x4,
|
||||
const void *cookie,
|
||||
void *handle,
|
||||
uint64_t flags)
|
||||
{
|
||||
switch (smc_fid) {
|
||||
|
||||
case TEGRA_SIP_AARCH_SWITCH:
|
||||
|
||||
/* clean up the high bits */
|
||||
x1 = (uint32_t)x1;
|
||||
x2 = (uint32_t)x2;
|
||||
|
||||
if (!x1 || x2 > NS_SWITCH_AARCH32) {
|
||||
ERROR("%s: invalid parameters\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* x1 = ns entry point */
|
||||
cm_set_elr_spsr_el3(NON_SECURE, x1,
|
||||
(x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64);
|
||||
|
||||
/* switch NS world mode */
|
||||
cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2);
|
||||
|
||||
INFO("CPU switched to AARCH%s mode\n",
|
||||
(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
|
||||
return 0;
|
||||
|
||||
default:
|
||||
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
|
||||
break;
|
||||
}
|
||||
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
#
|
||||
# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
TZDRAM_BASE := 0xF5C00000
|
||||
$(eval $(call add_define,TZDRAM_BASE))
|
||||
|
||||
PLATFORM_CLUSTER_COUNT := 1
|
||||
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
|
||||
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER := 2
|
||||
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
MAX_XLAT_TABLES := 3
|
||||
$(eval $(call add_define,MAX_XLAT_TABLES))
|
||||
|
||||
MAX_MMAP_REGIONS := 8
|
||||
$(eval $(call add_define,MAX_MMAP_REGIONS))
|
||||
|
||||
# platform files
|
||||
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132
|
||||
|
||||
BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
lib/cpus/aarch64/denver.S \
|
||||
${TEGRA_DRIVERS}/flowctrl/flowctrl.c \
|
||||
${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \
|
||||
${TEGRA_DRIVERS}/pmc/pmc.c \
|
||||
${SOC_DIR}/plat_psci_handlers.c \
|
||||
${SOC_DIR}/plat_sip_calls.c \
|
||||
${SOC_DIR}/plat_setup.c \
|
||||
${SOC_DIR}/plat_secondary.c
|
||||
Loading…
Add table
Reference in a new issue