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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <denver.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#define SB_CSR 0x0
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#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
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/* AARCH64 CPU reset vector */
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#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */
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#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */
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/* AARCH32 CPU reset vector */
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#define EVP_CPU_RESET_VECTOR 0x100
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extern void tegra_secure_entrypoint(void);
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/*
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* For T132, CPUs reset to AARCH32, so the reset vector is first
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* armv8_trampoline which does a warm reset to AARCH64 and starts
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* execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI.
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*/
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__aligned(8) const uint32_t armv8_trampoline[] = {
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0xE3A00003, /* mov r0, #3 */
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0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */
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0xEAFFFFFE, /* b . */
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};
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t val;
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uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint;
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/*
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* For T132, CPUs reset to AARCH32, so the reset vector is first
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* armv8_trampoline, which does a warm reset to AARCH64 and starts
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* execution at the address in SCRATCH34/SCRATCH35.
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*/
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INFO("Setting up T132 CPU boot\n");
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/* initial AARCH32 reset address */
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tegra_pmc_write_32(PMC_SECURE_SCRATCH22,
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(unsigned long)&armv8_trampoline);
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/* set AARCH32 exception vector (read to flush) */
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mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR,
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(unsigned long)&armv8_trampoline);
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val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR);
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/* setup secondary CPU vector */
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mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
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(reset_addr & 0xFFFFFFFF) | 1);
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val = reset_addr >> 32;
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mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
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/* configure PMC */
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tegra_pmc_cpu_setup(reset_addr);
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tegra_pmc_lock_cpu_vectors();
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}
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