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drivers: add tzc380 support
Add tzc380 support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
This commit is contained in:
Peng Fan
Bai Ping
parent
37e8ab5323
commit
46f9b2c3a2
4 changed files with 271 additions and 21 deletions
103
drivers/arm/tzc/tzc380.c
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103
drivers/arm/tzc/tzc380.c
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@ -0,0 +1,103 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <debug.h>
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#include <mmio.h>
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#include <stddef.h>
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#include <tzc380.h>
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struct tzc380_instance {
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uintptr_t base;
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uint8_t addr_width;
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uint8_t num_regions;
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};
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struct tzc380_instance tzc380;
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static unsigned int tzc380_read_build_config(uintptr_t base)
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{
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return mmio_read_32(base + TZC380_CONFIGURATION_OFF);
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}
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static void tzc380_write_action(uintptr_t base, tzc_action_t action)
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{
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mmio_write_32(base + ACTION_OFF, action);
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}
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static void tzc380_write_region_base_low(uintptr_t base, unsigned int region,
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unsigned int val)
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{
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mmio_write_32(base + REGION_SETUP_LOW_OFF(region), val);
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}
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static void tzc380_write_region_base_high(uintptr_t base, unsigned int region,
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unsigned int val)
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{
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mmio_write_32(base + REGION_SETUP_HIGH_OFF(region), val);
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}
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static void tzc380_write_region_attributes(uintptr_t base, unsigned int region,
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unsigned int val)
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{
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mmio_write_32(base + REGION_ATTRIBUTES_OFF(region), val);
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}
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void tzc380_init(uintptr_t base)
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{
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unsigned int tzc_build;
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assert(base != NULL);
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tzc380.base = base;
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/* Save values we will use later. */
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tzc_build = tzc380_read_build_config(tzc380.base);
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tzc380.addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) &
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BUILD_CONFIG_AW_MASK) + 1;
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tzc380.num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) &
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BUILD_CONFIG_NR_MASK) + 1;
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}
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static uint32_t addr_low(uintptr_t addr)
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{
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return (uint32_t)addr;
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}
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static uint32_t addr_high(uintptr_t addr __unused)
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{
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#if (UINTPTR_MAX == UINT64_MAX)
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return addr >> 32;
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#else
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return 0;
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#endif
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}
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/*
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* `tzc380_configure_region` is used to program regions into the TrustZone
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* controller.
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*/
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void tzc380_configure_region(uint8_t region, uintptr_t region_base, unsigned int attr)
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{
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assert(tzc380.base != NULL);
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assert(region < tzc380.num_regions);
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tzc380_write_region_base_low(tzc380.base, region, addr_low(region_base));
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tzc380_write_region_base_high(tzc380.base, region, addr_high(region_base));
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tzc380_write_region_attributes(tzc380.base, region, attr);
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}
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void tzc380_set_action(tzc_action_t action)
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{
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assert(tzc380.base != NULL);
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/*
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* - Currently no handler is provided to trap an error via interrupt
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* or exception.
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* - The interrupt action has not been tested.
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*/
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tzc380_write_action(tzc380.base, action);
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}
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159
include/drivers/arm/tzc380.h
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159
include/drivers/arm/tzc380.h
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@ -0,0 +1,159 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TZC380_H
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#define TZC380_H
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#include <tzc_common.h>
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#include <utils_def.h>
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#define TZC380_CONFIGURATION_OFF U(0x000)
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#define ACTION_OFF U(0x004)
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#define LOCKDOWN_RANGE_OFF U(0x008)
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#define LOCKDOWN_SELECT_OFF U(0x00C)
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#define INT_STATUS U(0x010)
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#define INT_CLEAR U(0x014)
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#define FAIL_ADDRESS_LOW_OFF U(0x020)
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#define FAIL_ADDRESS_HIGH_OFF U(0x024)
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#define FAIL_CONTROL_OFF U(0x028)
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#define FAIL_ID U(0x02c)
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#define SPECULATION_CTRL_OFF U(0x030)
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#define SECURITY_INV_EN_OFF U(0x034)
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#define REGION_SETUP_LOW_OFF(n) U(0x100 + (n) * 0x10)
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#define REGION_SETUP_HIGH_OFF(n) U(0x104 + (n) * 0x10)
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#define REGION_ATTRIBUTES_OFF(n) U(0x108 + (n) * 0x10)
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#define BUILD_CONFIG_AW_SHIFT 8
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#define BUILD_CONFIG_AW_MASK U(0x3f)
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#define BUILD_CONFIG_NR_SHIFT 0
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#define BUILD_CONFIG_NR_MASK U(0xf)
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#define ACTION_RV_SHIFT 0
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#define ACTION_RV_MASK U(0x3)
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#define ACTION_RV_LOWOK U(0x0)
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#define ACTION_RV_LOWERR U(0x1)
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#define ACTION_RV_HIGHOK U(0x2)
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#define ACTION_RV_HIGHERR U(0x3)
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/* Speculation is enabled by default. */
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#define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
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#define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
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#define INT_STATUS_OVERRUN_SHIFT 1
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#define INT_STATUS_OVERRUN_MASK U(0x1)
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#define INT_STATUS_STATUS_SHIFT 0
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#define INT_STATUS_STATUS_MASK U(0x1)
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#define INT_CLEAR_CLEAR_SHIFT 0
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#define INT_CLEAR_CLEAR_MASK U(0x1)
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#define TZC380_COMPONENT_ID U(0xb105f00d)
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#define TZC380_PERIPH_ID_LOW U(0x001bb380)
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#define TZC380_PERIPH_ID_HIGH U(0x00000004)
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#define TZC_SP_NS_W BIT_32(0)
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#define TZC_SP_NS_R BIT_32(1)
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#define TZC_SP_S_W BIT_32(2)
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#define TZC_SP_S_R BIT_32(3)
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#define TZC_ATTR_SP_SHIFT 28
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#define TZC_ATTR_SP_ALL ((TZC_SP_S_W | TZC_SP_S_R | TZC_SP_NS_W | \
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TZC_SP_NS_R) << TZC_ATTR_SP_SHIFT)
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#define TZC_ATTR_SP_S_RW ((TZC_SP_S_W | TZC_SP_S_R) << \
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TZC_ATTR_SP_SHIFT)
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#define TZC_ATTR_SP_NS_RW ((TZC_SP_NS_W | TZC_SP_NS_R) << \
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TZC_ATTR_SP_SHIFT)
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#define TZC_REGION_SIZE_32K U(0xe)
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#define TZC_REGION_SIZE_64K U(0xf)
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#define TZC_REGION_SIZE_128K U(0x10)
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#define TZC_REGION_SIZE_256K U(0x11)
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#define TZC_REGION_SIZE_512K U(0x12)
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#define TZC_REGION_SIZE_1M U(0x13)
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#define TZC_REGION_SIZE_2M U(0x14)
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#define TZC_REGION_SIZE_4M U(0x15)
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#define TZC_REGION_SIZE_8M U(0x16)
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#define TZC_REGION_SIZE_16M U(0x17)
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#define TZC_REGION_SIZE_32M U(0x18)
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#define TZC_REGION_SIZE_64M U(0x19)
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#define TZC_REGION_SIZE_128M U(0x1a)
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#define TZC_REGION_SIZE_256M U(0x1b)
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#define TZC_REGION_SIZE_512M U(0x1c)
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#define TZC_REGION_SIZE_1G U(0x1d)
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#define TZC_REGION_SIZE_2G U(0x1e)
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#define TZC_REGION_SIZE_4G U(0x1f)
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#define TZC_REGION_SIZE_8G U(0x20)
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#define TZC_REGION_SIZE_16G U(0x21)
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#define TZC_REGION_SIZE_32G U(0x22)
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#define TZC_REGION_SIZE_64G U(0x23)
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#define TZC_REGION_SIZE_128G U(0x24)
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#define TZC_REGION_SIZE_256G U(0x25)
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#define TZC_REGION_SIZE_512G U(0x26)
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#define TZC_REGION_SIZE_1T U(0x27)
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#define TZC_REGION_SIZE_2T U(0x28)
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#define TZC_REGION_SIZE_4T U(0x29)
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#define TZC_REGION_SIZE_8T U(0x2a)
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#define TZC_REGION_SIZE_16T U(0x2b)
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#define TZC_REGION_SIZE_32T U(0x2c)
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#define TZC_REGION_SIZE_64T U(0x2d)
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#define TZC_REGION_SIZE_128T U(0x2e)
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#define TZC_REGION_SIZE_256T U(0x2f)
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#define TZC_REGION_SIZE_512T U(0x30)
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#define TZC_REGION_SIZE_1P U(0x31)
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#define TZC_REGION_SIZE_2P U(0x32)
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#define TZC_REGION_SIZE_4P U(0x33)
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#define TZC_REGION_SIZE_8P U(0x34)
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#define TZC_REGION_SIZE_16P U(0x35)
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#define TZC_REGION_SIZE_32P U(0x36)
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#define TZC_REGION_SIZE_64P U(0x37)
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#define TZC_REGION_SIZE_128P U(0x38)
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#define TZC_REGION_SIZE_256P U(0x39)
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#define TZC_REGION_SIZE_512P U(0x3a)
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#define TZC_REGION_SIZE_1E U(0x3b)
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#define TZC_REGION_SIZE_2E U(0x3c)
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#define TZC_REGION_SIZE_4E U(0x3d)
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#define TZC_REGION_SIZE_8E U(0x3e)
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#define TZC_REGION_SIZE_16E U(0x3f)
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#define TZC_REGION_SIZE_SHIFT 0x1
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#define TZC_REGION_SIZE_MASK U(0x7e)
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#define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT)
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#define TZC_ATTR_REGION_EN_SHIFT 0x0
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#define TZC_ATTR_REGION_EN_MASK U(0x1)
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#define TZC_ATTR_REGION_EN
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#define TZC_ATTR_REGION_ENABLE U(0x1)
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#define TZC_ATTR_REGION_DISABLE U(0x0)
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#define REGION_MAX 16
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void tzc380_init(uintptr_t base);
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void tzc380_configure_region(uint8_t region,
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uintptr_t region_base,
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unsigned int attr);
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void tzc380_set_action(tzc_action_t action);
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static inline void tzc_init(uintptr_t base)
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{
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tzc380_init(base);
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}
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static inline void tzc_configure_region(uint8_t region,
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uintptr_t region_base,
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unsigned int attr)
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{
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tzc380_configure_region(region, region_base, attr);
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}
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static inline void tzc_set_action(tzc_action_t action)
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{
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tzc380_set_action(action);
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}
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#endif /* TZC380_H */
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@ -7,8 +7,6 @@
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#ifndef SOC_TZASC_H
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#define SOC_TZASC_H
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#include "tzc380.h"
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#define MAX_NUM_TZC_REGION 3
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/* TZASC related constants */
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#define CCI_TERMINATE_BARRIER_TX 0x8
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#define CONFIG_SYS_FSL_TZASC_ADDR 0x1500000
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struct tzc380_reg {
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unsigned int secure;
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unsigned int enabled;
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unsigned int low_addr;
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unsigned int high_addr;
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unsigned int size;
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unsigned int sub_mask;
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};
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/* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */
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static const struct tzc380_reg tzc380_reg_list[] = {
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TZC380_H
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#define TZC380_H
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struct tzc380_reg {
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unsigned int secure;
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unsigned int enabled;
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unsigned int low_addr;
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unsigned int high_addr;
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unsigned int size;
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unsigned int sub_mask;
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};
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#endif /* TZC380_H */
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