mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
1d49112b2a
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
75 lines
2 KiB
C
75 lines
2 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <tegra_private.h>
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#define NS_SWITCH_AARCH32 1
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#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
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/*******************************************************************************
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* Tegra132 SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_AARCH_SWITCH 0x82000004
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/*******************************************************************************
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* SPSR settings for AARCH32/AARCH64 modes
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******************************************************************************/
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#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \
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DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)
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#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
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/*******************************************************************************
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* This function is responsible for handling all T132 SiP calls
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******************************************************************************/
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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const void *cookie,
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void *handle,
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uint64_t flags)
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{
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switch (smc_fid) {
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case TEGRA_SIP_AARCH_SWITCH:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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if (!x1 || x2 > NS_SWITCH_AARCH32) {
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ERROR("%s: invalid parameters\n", __func__);
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return -EINVAL;
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}
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/* x1 = ns entry point */
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cm_set_elr_spsr_el3(NON_SECURE, x1,
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(x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64);
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/* switch NS world mode */
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cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2);
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INFO("CPU switched to AARCH%s mode\n",
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(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
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return 0;
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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}
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return -ENOTSUP;
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}
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