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perf(cpus): inline the reset function

Browse source 
Similar to the cpu_rev_var and cpu_ger_rev_var functions, inline the
call_reset_handler handler. This way we skip the costly branch at no
extra cost as this is the only place where this is called.

While we're at it, drop the options for CPU_NO_RESET_FUNC. The only cpus
that need that are virtual cpus which can spare the tiny bit of
performance lost. The rest are real cores which can save on the check
for zero.

Now is a good time to put the assert for a missing cpu in the
get_cpu_ops_ptr function so that it's a bit better encapsulated.

Change-Id: Ia7c3dcd13b75e5d7c8bafad4698994ea65f42406
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
Boyan Karatotev 2024-11-19 11:27:01 +00:00
parent 36eeb59f9e
commit 0d020822ae
13 changed files with 64 additions and 72 deletions
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6
docs/design/firmware-design.rst
View file

@ -247,7 +247,7 @@ BL1 performs minimal architectural initialization as follows.
- CPU initialization
BL1 calls the ``reset_handler()`` function which in turn calls the CPU
BL1 calls the ``reset_handler`` macro/function which in turn calls the CPU
specific reset handler function (see the section: "CPU specific operations
framework").
@ -1337,7 +1337,7 @@ Guidelines for Reset Handlers
TF-A implements a framework that allows CPU and platform ports to perform
actions very early after a CPU is released from reset in both the cold and warm
boot paths. This is done by calling the ``reset_handler()`` function in both
boot paths. This is done by calling the ``reset_handler`` macro/function in both
the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
handling functions.
@ -2904,7 +2904,7 @@ kernel at boot time. These can be found in the ``fdts`` directory.
--------------
*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.*
.. _SMCCC: https://developer.arm.com/docs/den0028/latest
.. _PSCI: https://developer.arm.com/documentation/den0022/latest/

23
include/arch/aarch64/asm_macros.S
View file

@ -8,6 +8,7 @@
#include <arch.h>
#include <common/asm_macros_common.S>
#include <lib/cpus/cpu_ops.h>
#include <lib/spinlock.h>
/*
@ -340,4 +341,26 @@
mrs \reg, ID_AA64ISAR2_EL1
ands \reg, \reg, #(ID_AA64ISAR2_SYSREG128_MASK << ID_AA64ISAR2_SYSREG128_SHIFT)
.endm
.macro call_reset_handler
#if !(defined(IMAGE_BL2) && ENABLE_RME)
/* ---------------------------------------------------------------------
* It is a cold boot.
* Perform any processor specific actions upon reset e.g. cache, TLB
* invalidations etc.
* ---------------------------------------------------------------------
*/
/* The plat_reset_handler can clobber x0 - x18, x30 */
bl plat_reset_handler
/* Get the matching cpu_ops pointer */
bl get_cpu_ops_ptr
/* Get the cpu_ops reset handler */
ldr x2, [x0, #CPU_RESET_FUNC]
/* The cpu_ops reset handler can clobber x0 - x19, x30 */
blr x2
#endif
.endm
#endif /* ASM_MACROS_S */

4
include/arch/aarch64/el2_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -293,7 +293,7 @@
* invalidations etc.
* ---------------------------------------------------------------------
*/
bl reset_handler
call_reset_handler
el2_arch_init_common

12
include/arch/aarch64/el3_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -219,15 +219,7 @@
msr vbar_el3, x0
isb
#if !(defined(IMAGE_BL2) && ENABLE_RME)
/* ---------------------------------------------------------------------
* It is a cold boot.
* Perform any processor specific actions upon reset e.g. cache, TLB
* invalidations etc.
* ---------------------------------------------------------------------
*/
bl reset_handler
#endif
call_reset_handler
el3_arch_init_common

5
include/lib/cpus/aarch32/cpu_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -48,8 +48,7 @@
* _midr:
* Numeric value expected to read from CPU's MIDR
* _resetfunc:
* Reset function for the CPU. If there's no CPU reset function,
* specify CPU_NO_RESET_FUNC
* Reset function for the CPU
* _power_down_ops:
* Comma-separated list of functions to perform power-down
* operatios on the CPU. At least one, and up to

3
include/lib/cpus/aarch64/cpu_macros.S
View file

@ -49,8 +49,7 @@
* _midr:
* Numeric value expected to read from CPU's MIDR
* _resetfunc:
* Reset function for the CPU. If there's no CPU reset function,
* specify CPU_NO_RESET_FUNC
* Reset function for the CPU.
* _extra1:
* This is a placeholder for future per CPU operations. Currently,
* some CPUs use this entry to set a test function to determine if

2
include/lib/cpus/cpu_ops.h
View file

@ -21,8 +21,6 @@
/* The number of CPU operations allowed */
#define CPU_MAX_PWR_DWN_OPS 2
/* Special constant to specify that CPU has no reset function */
#define CPU_NO_RESET_FUNC 0
#if __aarch64__
#define CPU_NO_EXTRA1_FUNC 0

7
lib/cpus/aarch32/aem_generic.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -40,8 +40,11 @@ func aem_generic_cluster_pwr_dwn
b dcsw_op_all
endfunc aem_generic_cluster_pwr_dwn
func aem_generic_reset_func
bx lr
endfunc aem_generic_reset_func
/* cpu_ops for Base AEM FVP */
declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
declare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \
aem_generic_core_pwr_dwn, \
aem_generic_cluster_pwr_dwn

5
lib/cpus/aarch64/a64fx.S
View file

@ -29,12 +29,15 @@ endfunc a64fx_cluster_pwr_dwn
a64fx_regs: /* The ascii list of register names to be reported */
.asciz ""
cpu_reset_func_start a64fx
cpu_reset_func_end a64fx
func a64fx_cpu_reg_dump
adr x6, a64fx_regs
ret
endfunc a64fx_cpu_reg_dump
declare_cpu_ops a64fx, A64FX_MIDR, CPU_NO_RESET_FUNC \
declare_cpu_ops a64fx, A64FX_MIDR, a64fx_reset_func \
a64fx_core_pwr_dwn, \
a64fx_cluster_pwr_dwn

9
lib/cpus/aarch64/aem_generic.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -74,6 +74,9 @@ func aem_generic_cluster_pwr_dwn
b dcsw_op_all
endfunc aem_generic_cluster_pwr_dwn
cpu_reset_func_start aem_generic
cpu_reset_func_end aem_generic
/* ---------------------------------------------
* This function provides cpu specific
* register information for crash reporting.
@ -94,11 +97,11 @@ endfunc aem_generic_cpu_reg_dump
/* cpu_ops for Base AEM FVP */
declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
declare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \
aem_generic_core_pwr_dwn, \
aem_generic_cluster_pwr_dwn
/* cpu_ops for Foundation FVP */
declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \
declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, aem_generic_reset_func, \
aem_generic_core_pwr_dwn, \
aem_generic_cluster_pwr_dwn

49
lib/cpus/aarch64/cpu_helpers.S
View file

@ -14,47 +14,6 @@
#include <lib/cpus/errata.h>
#include <lib/el3_runtime/cpu_data.h>
/* Reset fn is needed in BL at reset vector */
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || \
(defined(IMAGE_BL2) && RESET_TO_BL2)
/*
* The reset handler common to all platforms. After a matching
* cpu_ops structure entry is found, the correponding reset_handler
* in the cpu_ops is invoked.
* Clobbers: x0 - x19, x30
*/
.globl reset_handler
func reset_handler
mov x19, x30
/* The plat_reset_handler can clobber x0 - x18, x30 */
bl plat_reset_handler
/* Get the matching cpu_ops pointer */
bl get_cpu_ops_ptr
#if ENABLE_ASSERTIONS
/*
* Assert if invalid cpu_ops obtained. If this is not valid, it may
* suggest that the proper CPU file hasn't been included.
*/
cmp x0, #0
ASM_ASSERT(ne)
#endif
/* Get the cpu_ops reset handler */
ldr x2, [x0, #CPU_RESET_FUNC]
mov x30, x19
cbz x2, 1f
/* The cpu_ops reset handler can clobber x0 - x19, x30 */
br x2
1:
ret
endfunc reset_handler
#endif
#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
/*
* void prepare_cpu_pwr_dwn(unsigned int power_level)
@ -212,6 +171,14 @@ search_def_ptr:
mov x2, #0
b 1b
error_exit:
#endif
#if ENABLE_ASSERTIONS
/*
* Assert if invalid cpu_ops obtained. If this is not valid, it may
* suggest that the proper CPU file hasn't been included.
*/
cmp x0, #0
ASM_ASSERT(ne)
#endif
ret
endfunc get_cpu_ops_ptr

4
lib/cpus/aarch64/generic.S
View file

@ -80,7 +80,9 @@ endfunc generic_cluster_pwr_dwn
* ---------------------------------------------
*/
.equ generic_cpu_reg_dump, 0
.equ generic_reset_func, 0
cpu_reset_func_start generic
cpu_reset_func_end generic
declare_cpu_ops generic, AARCH64_GENERIC_MIDR, \
generic_reset_func, \

7
lib/cpus/aarch64/qemu_max.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -47,6 +47,9 @@ func qemu_max_cluster_pwr_dwn
b dcsw_op_all
endfunc qemu_max_cluster_pwr_dwn
cpu_reset_func_start qemu_max
cpu_reset_func_end qemu_max
/* ---------------------------------------------
* This function provides cpu specific
* register information for crash reporting.
@ -67,6 +70,6 @@ endfunc qemu_max_cpu_reg_dump
/* cpu_ops for QEMU MAX */
declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \
declare_cpu_ops qemu_max, QEMU_MAX_MIDR, qemu_max_reset_func, \
qemu_max_core_pwr_dwn, \
qemu_max_cluster_pwr_dwn