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https://github.com/ARM-software/arm-trusted-firmware.git
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0d020822ae
Similar to the cpu_rev_var and cpu_ger_rev_var functions, inline the call_reset_handler handler. This way we skip the costly branch at no extra cost as this is the only place where this is called. While we're at it, drop the options for CPU_NO_RESET_FUNC. The only cpus that need that are virtual cpus which can spare the tiny bit of performance lost. The rest are real cores which can save on the check for zero. Now is a good time to put the assert for a missing cpu in the get_cpu_ops_ptr function so that it's a bit better encapsulated. Change-Id: Ia7c3dcd13b75e5d7c8bafad4698994ea65f42406 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
107 lines
2.8 KiB
ArmAsm
107 lines
2.8 KiB
ArmAsm
/*
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* Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <aem_generic.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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func aem_generic_core_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* AEM model supports L3 caches in which case L2
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* will be private per core caches and flush
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* from L1 to L2 is not sufficient.
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* ---------------------------------------------
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*/
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mrs x1, clidr_el1
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/* ---------------------------------------------
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* Check if L3 cache is implemented.
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* ---------------------------------------------
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*/
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tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3)
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/* ---------------------------------------------
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* There is no L3 cache, flush L1 to L2 only.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b.eq dcsw_op_level1
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mov x18, x30
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/* ---------------------------------------------
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* Flush L1 cache to L2.
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* ---------------------------------------------
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*/
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bl dcsw_op_level1
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mov x30, x18
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/* ---------------------------------------------
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* Flush L2 cache to L3.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b dcsw_op_level2
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endfunc aem_generic_core_pwr_dwn
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func aem_generic_cluster_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* Flush all caches to PoC.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b dcsw_op_all
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endfunc aem_generic_cluster_pwr_dwn
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cpu_reset_func_start aem_generic
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cpu_reset_func_end aem_generic
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/* ---------------------------------------------
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* This function provides cpu specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.aem_generic_regs, "aS"
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aem_generic_regs: /* The ascii list of register names to be reported */
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.asciz "" /* no registers to report */
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func aem_generic_cpu_reg_dump
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adr x6, aem_generic_regs
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ret
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endfunc aem_generic_cpu_reg_dump
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/* cpu_ops for Base AEM FVP */
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \
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aem_generic_core_pwr_dwn, \
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aem_generic_cluster_pwr_dwn
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/* cpu_ops for Foundation FVP */
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declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, aem_generic_reset_func, \
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aem_generic_core_pwr_dwn, \
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aem_generic_cluster_pwr_dwn
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