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0d020822ae
Similar to the cpu_rev_var and cpu_ger_rev_var functions, inline the call_reset_handler handler. This way we skip the costly branch at no extra cost as this is the only place where this is called. While we're at it, drop the options for CPU_NO_RESET_FUNC. The only cpus that need that are virtual cpus which can spare the tiny bit of performance lost. The rest are real cores which can save on the check for zero. Now is a good time to put the assert for a missing cpu in the get_cpu_ops_ptr function so that it's a bit better encapsulated. Change-Id: Ia7c3dcd13b75e5d7c8bafad4698994ea65f42406 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
197 lines
5.2 KiB
ArmAsm
197 lines
5.2 KiB
ArmAsm
/*
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* Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CPU_MACROS_S
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#define CPU_MACROS_S
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#include <lib/cpus/cpu_ops.h>
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#include <lib/cpus/errata.h>
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/*
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* Write given expressions as words
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*
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* _count:
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* Write at least _count words. If the given number of expressions
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* is less than _count, repeat the last expression to fill _count
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* words in total
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* _rest:
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* Optional list of expressions. _this is for parameter extraction
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* only, and has no significance to the caller
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*
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* Invoked as:
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* fill_constants 2, foo, bar, blah, ...
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*/
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.macro fill_constants _count:req, _this, _rest:vararg
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.ifgt \_count
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/* Write the current expression */
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.ifb \_this
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.error "Nothing to fill"
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.endif
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.word \_this
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/* Invoke recursively for remaining expressions */
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.ifnb \_rest
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fill_constants \_count-1, \_rest
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.else
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fill_constants \_count-1, \_this
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.endif
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.endif
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.endm
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/*
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* Declare CPU operations
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*
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* _name:
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* Name of the CPU for which operations are being specified
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* _midr:
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* Numeric value expected to read from CPU's MIDR
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* _resetfunc:
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* Reset function for the CPU
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* _power_down_ops:
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* Comma-separated list of functions to perform power-down
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* operatios on the CPU. At least one, and up to
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* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
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* Starting at power level 0, these functions shall handle power
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* down at subsequent power levels. If there aren't exactly
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* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
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* used to handle power down at subsequent levels
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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_power_down_ops:vararg
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.section .cpu_ops, "a"
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.align 2
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.type cpu_ops_\_name, %object
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.word \_midr
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#if defined(IMAGE_AT_EL3)
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.word \_resetfunc
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#endif
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#ifdef IMAGE_BL32
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/* Insert list of functions */
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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#endif
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/*
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* It is possible (although unlikely) that a cpu may have no errata in
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* code. In that case the start label will not be defined. The list is
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* inteded to be used in a loop, so define it as zero-length for
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* predictable behaviour. Since this macro is always called at the end
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* of the cpu file (after all errata have been parsed) we can be sure
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* that we are at the end of the list. Some cpus call the macro twice,
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* so only do this once.
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*/
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.pushsection .rodata.errata_entries
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.ifndef \_name\()_errata_list_start
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\_name\()_errata_list_start:
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.endif
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/* some call this multiple times, so only do this once */
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.ifndef \_name\()_errata_list_end
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\_name\()_errata_list_end:
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.endif
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.popsection
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/* and now put them in cpu_ops */
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.word \_name\()_errata_list_start
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.word \_name\()_errata_list_end
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#if REPORT_ERRATA
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.ifndef \_name\()_cpu_str
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/*
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* Place errata reported flag, and the spinlock to arbitrate access to
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* it in the data section.
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*/
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.pushsection .data
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define_asm_spinlock \_name\()_errata_lock
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\_name\()_errata_reported:
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.word 0
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.popsection
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/* Place CPU string in rodata */
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.pushsection .rodata
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\_name\()_cpu_str:
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.asciz "\_name"
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.popsection
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.endif
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.word \_name\()_cpu_str
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#ifdef IMAGE_BL32
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/* Pointers to errata lock and reported flag */
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.word \_name\()_errata_lock
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.word \_name\()_errata_reported
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#endif
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#endif
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.endm
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/*
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* Helper macro that reads the part number of the current CPU and jumps
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* to the given label if it matches the CPU MIDR provided.
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*
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* Clobbers: r0-r1
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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ldcopr r0, MIDR
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ubfx r0, r0, #MIDR_PN_SHIFT, #12
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ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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cmp r0, r1
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beq \_label
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.endm
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/*
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* NOTE an erratum and CVE id could clash. However, both numbers are very large
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* and the probablity is minuscule. Working around this makes code very
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* complicated and extremely difficult to read so it is not considered. In the
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* unlikely event that this does happen, prepending the CVE id with a 0 should
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* resolve the conflict
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*/
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/*
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* Add an entry for this erratum to the errata framework
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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*
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* _cve:
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* Whether erratum is a CVE. CVE year if yes, 0 otherwise
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*
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* _id:
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* Erratum or CVE number. Please combine with the previous field with the
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* ERRATUM or CVE macros
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*
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* _chosen:
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* Compile time flag on whether the erratum is included
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*
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* _special:
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* The special non-standard name of an erratum
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*/
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.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _special
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.pushsection .rodata.errata_entries
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.align 2
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.ifndef \_cpu\()_errata_list_start
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\_cpu\()_errata_list_start:
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.endif
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/* unused on AArch32, maintain for portability */
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.word 0
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/* TODO(errata ABI): this prevents all checker functions from
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* being optimised away. Can be done away with unless the ABI
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* needs them */
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.ifnb \_special
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.word check_errata_\_special
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.elseif \_cve
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.word check_errata_cve_\_cve\()_\_id
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.else
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.word check_errata_\_id
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.endif
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/* Will fit CVEs with up to 10 character in the ID field */
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.word \_id
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.hword \_cve
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.byte \_chosen
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/* TODO(errata ABI): mitigated field for known but unmitigated
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* errata*/
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.byte 0x1
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.popsection
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.endm
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#endif /* CPU_MACROS_S */
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