* Initial UFS PHY driver
* Support for SM8150 (clock and pinctrl)
* Allow writing configuration to PMIC GPIOs again
* Support for configuring "special" pins (e.g. UFS reset or sdhc pins)
* Support for "clk dump" command to decode various clocks.
The series "rockchip: Add efuse and otp support to more SoCs" [1],
merged in v2023.04, refactored and extended the Rockchip efuse and otp
driver to support reading eFUSE/OTP for all supported Rockchip SoCs.
Due to use of different licenses the drivers were never combined into a
single driver, however anything non SoC specific should be applied to
both drivers.
The commit fe38b88453 ("rockchip: Provided SPL control over efuse
presence") changed Makefile options for only one of the two drivers,
apply same change to keep these two drivers in sync.
[1] https://lore.kernel.org/r/20230222224436.1570224-1-jonas@kwiboo.se/
Fixes: fe38b88453 ("rockchip: Provided SPL control over efuse presence")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add support for dumping a few of the clocks used on Qualcomm platforms.
Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making
it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of
qcom-<soc>.c.
The "clk dump" command should print the states of all the gates, GPLLs
and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator
* Takes in some fairly arbitrary high freq clock (configurable clock
source and options for taking just even pulses and other things)
* Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary
8 or 16-bit values (depending on the RCG), and d is a number (with
support for .5 offsets).
GPLL: Global Phase Locked Loop
* Crystal as input
* integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock
* Put between RCGs and the peripherals they power
* Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the
numbers should roughly line up by they're likely to be out by a handful
of MHz. They output is formatted so that it can be pasted directly into
the python interpreter.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This reverts commit 19f000b72b.
The bug in writing was caused by a long-standing error in the SPMI
driver which has since been fixed - c2de620d64 ("spmi: msm: fix
version 5 support"). We can safely enable writing GPIO configuration
now.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8250 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Leverage the data introduced in the struct msm_special_pin_data to allow
setting the gpio direction and value if supported by the pin data.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Add Qualcomm QMP UFS PHY driver which is available on the following
Snapdragon SoCs - SDM845, SM8250, SM8550 and SM8650 SoCs.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Import Qualcomm QMP phy related header files from Linux v6.11-rc7,
limit to headers needed to setup QMP v2 to v6 UFS PHYs.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Add pinctrl and GPIO driver for SM8150. Driver code is based on the
similar U-Boot drivers. All constants are taken from the corresponding
Linux driver. This drivers differs from the similar U-Boot drivers,
because SM8150 SoC have different function IDs for the same functions
on different pins.
Co-authored-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Julius Lehmann <lehmanju@devpi.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Add clock, reset and power domain driver for SM8150. Driver code is
based on the similar U-Boot drivers. All constants are taken from the
corresponding Linux driver.
This driver supports clock rate setting only debug UART,
RGMII/Ethernet modules and USB controller.
Co-authored-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Julius Lehmann <lehmanju@devpi.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
The DA9063 PMIC is a multi-function device that provides
regulator, watchdog, RTC, and ON key functionalities.
Add support for the DA9063 PMIC watchdog functionality.
Based on the 6.11 kernel drivers/watchdog/da9063_wdt.c driver.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
When supporting partition reset for SoC such as i.MX95 , the Linux
Kernel may have configured the tuning, while after force reset by
wdog or else, uboot CMD0 will never pass unless config RSTT to reset
tuning logic.
Since RSTA and RSTT are independent, so need both to be reseted in the
controller.
Acked-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The memory of priv and plat are leaked if max_bus_width is wrong.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The plat->cfg is wrongly memset to 0, so the host_caps value configured
in fsl_esdhc_initialize is reset. Remove the unnecessary memset since
plat is allocated via calloc.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
According to SD and MMC spec, 74 clocks must be sent to device after
power stable. This is need in reinit ops for DM MMC or init ops for
non-DM MMC after power cycle.
So set the INTIA to send 80 clocks in esdhc_init_common and move
its calling from probe to reinit.
However, on 8MQ EVK and 8QXP MEK with some brands of SD cards, sending
80 clocks may not work well.
The root cause is related with power up time. According to spec, after
power stable, host shall supply at least 74 SD clocks to the SD card with
the maximum of 1ms. However, the power ram up time is related with the
characteristic of SD card. At the moment of sending 74 SD clocks, the
power probably not ram up to the operating level on the problematic
cards. Then cause the cards not ready.
This patch changes to send SD clock with 1ms duration to replace 80
SD clocks (0.2ms at 400Khz clock).
This way meets the spec requirement as well, and adds the margin for
power ram up time to be compatible with the problematic SD cards.
This is also aligned with implementation which has FORCE clock
always on.
Reviewed-and-tested-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
With partition reset supported for i.MX8QM/QXP/95 and etc, when linux
mmc runtime suspended, the mmc clks are gated off. While at same time
system controller reset Cortex-A cores because of various reasons(
WDOG timeout and etc), with SPL run again, only enable PER clk is not
enough, also need to enable AHB/IPG clk, here use clk bulk API to enable
all the clocks.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
So we can disable to build ADP5585 in SPL to save size
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
u-boot-dfu-next-20241003
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/22516
DFU:
- Reinitialize only if dfu_alt_info changed
USB Gadget:
- New usb gadget driver for Renesas USBHS
- Simplify kconfig deps for CMD_USB_MASS_STORAGE
Android:
- Provide bootloader version to android via kernel commandline
This driver should not generally be present in SPL, even if misc devices
are enabled. Update the Makefile rule accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow MMC init when clock support is not enabled in a particular phase.
Refactor the setting of priv->emmc_clk so it is a bit clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
A write to the TX buffer is performed before entering the loop to "avoid
clock starvation". This sometimes results in subsequent writes in
davinci_spi_xfer_data() to occur while the TXFULL bit is asserted,
leading to write failures.
Remove the preload of the TX buffer.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
When SPL_FS_LOADER is set to y and FS_LOADER is not enabled, the SPL build
fails with the following errors:
AR spl/boot/built-in.o
LD spl/u-boot-spl
arm-none-linux-gnueabihf-ld.bfd: drivers/misc/fs_loader.o: in function
`fw_get_filesystem_firmware':
/u-boot/drivers/misc/fs_loader.c:162: undefined reference to
`fs_set_blk_dev'
arm-none-linux-gnueabihf-ld.bfd: /home/frh/tdx/src/u-boot/drivers/misc/
fs_loader.c:185: undefined reference to `fs_read'
arm-none-linux-gnueabihf-ld.bfd: drivers/misc/fs_loader.o: in function
`select_fs_dev':
/u-boot/drivers/misc/fs_loader.c:89: undefined reference to
`fs_set_blk_dev_with_part'
make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make: *** [Makefile:2055: spl/u-boot-spl] Error 2
Fix it by replacing the FS_LOADER with SPL_FS_LOADER in the Makefile, so
the fs.c with the necessary function definitions are compiled.
Fixes: b071a07743 ("drivers: misc: Makefile: Enable fs_loader compilation at SPL Level")
Suggested-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Add UDC driver for Renesas USBHS controller found in R-Car Gen3 SoCs.
This is mostly ported from the Linux kernel, with additional porting
glue. The code has been synchronized with 1b4861e32e46 ("Linux 6.9.3")
and cleaned up and ported to DM since the original implementation by
Vitaliy.
Signed-off-by: Vitaliy Vasylskyy <vitaliy.vasylskyy@globallogic.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240908230654.286062-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
I'm trying to use dfu-util for bootstrapping an stm32mp board. It
mostly works fine, but something goes horribly wrong as soon as I make
use of the ability to run arbitrary u-boot shell commands. The shell
commands themselves work fine, but the heuristic "dfu_alt_info may
have changed, we have to reinit" seems to cause the board and/or my
host machine to go into some bad state, and further dfu-util commands
fail.
U-Boot already has a mechanism whereby C code can be told about
changes to specific environment variables. So instead of always doing
re-init, add a hook to the dfu_alt_info variable so that we only do
set dfu_reinit_needed if the commands actually did modify that
variable.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240911133900.1444083-1-rasmus.villemoes@prevas.dk
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Both regulators_enable_boot_on/off() are unused and superseded by
regulator uclass regulator_post_probe(). Remove both functions.
Signed-off-by: Marek Vasut <marex@denx.de>
Turn regulators_enable_boot_on() and regulators_enable_boot_off() into
empty functions. Implement matching functionality in regulator_post_probe()
instead. The regulator_post_probe() is called for all regulators after they
probe, and regulators that have regulator-always-on or regulator-boot-on DT
properties now always probe due to DM_FLAG_PROBE_AFTER_BIND being set on
such regulators in regulator_post_bind().
Finally, fold regulator_unset() functionality into regulator_autoset().
Signed-off-by: Marek Vasut <marex@denx.de>
In case a regulator DT node contains regulator-always-on or regulator-boot-on
property, make sure the regulator gets correctly configured by U-Boot on start
up. Unconditionally probe such regulator drivers. This is a preparatory patch
for introduction of .regulator_post_probe() which would trigger the regulator
configuration.
Parsing of regulator-always-on and regulator-boot-on DT property has been
moved to regulator_post_bind() as the information is required early, the
rest of the DT parsing has been kept in regulator_pre_probe() to avoid
slowing down the boot process.
Signed-off-by: Marek Vasut <marex@denx.de>
Transfer initiation and completion for the non-zero Endpoints are
handled by cdns3_ep_run_transfer() and cdns3_transfer_completed()
respectively.
Failing to flush the cache associated with the TRB Pool within
cdns3_ep_run_transfer() results in the transfers never being initiated.
Similarly, failing to invalidate the cache associated with the TRB pool
within cdns3_transfer_completed() results in the transfers never being
completed.
Fix this.
Fixes: 7e91f6ccdc ("usb: Add Cadence USB3 host and gadget driver")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The buck variable is zero based, i.e. buck=0 match BUCK1 in datasheet.
Remove any buck + 1 calculation to be more consistent in usage of the
buck variable across the different RK8xx variants in the driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Wrong POWER_EN reg is used to get and set enabled state for the RK806
buck 4 and 8 regulators, also wrong POWER_SLP_EN0 bit is used for
suspend state for the RK806 buck 1-8 regulators.
Fix this by not adding one to the zero based buck variable.
Fixes: f172575d92 ("power: rk8xx: add support for RK806")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
dev_get_driver_ops() may return NULL when the udevice is invalid.
Move the ops check to top of functions to consistently return -ENOSYS
when ops is unimplemented and prevent trying to access uclass plat data,
also add missing NULL checks to suspend ops.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
On some boards a PMIC regulator is flagged with regulator-on-in-suspend
and does not define any suspend or max microvolt, e.g. on Radxa ROCK 3A:
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
This result in suspend_uV having the value -ENODATA after probe.
This negative voltage, -ENODATA, gets missinterpreted and result in an
unexpected voltage being set by autoset.
E.g. on Radxa ROCK 3A the vcc_ddr regulator by default have a normal and
suspend voltage value of 0.5v. However, due to this missinterpretation
the suspend voltage end up beind set to 0.5625v instead.
Fix this by skip calling regulator_set_suspend_value() in autoset and
also protect calling set value ops when input value is -ENODATA.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
After FEC is halted by calling fec_halt callback, we should not continue
receiving packet. Otherwise it will process previous pending interrupts
on EIR register and uses wrong rbd index as this has been reset to 0.
The GRA interrupt which is triggered by issuing graceful stop command to
FEC transmitter in fec_halt is processed in this case. It causes wrong
receive buffer descriptors be used by FEC in next time.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX93 FEC ENET port supports two mode: RGMII and RMII. For RGMII,
there is an internal /2 divider, so the freq needs to set with (*2),
otherwise the speed will not reach 1G and cause communication error
in some network environments. For RMII, the clk path is
ccm -> enet tx_clk pin -> pad loop back to enet, no /2 divider.
So fix for RGMII mode with freq multiplied by 2.
Fixes: 09de565f76 ("net: fec_mxc: support i.MX93")
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
