Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-24 06:24:17 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

mmc: rockchip: Allow clocks to be missing

Browse source 
Allow MMC init when clock support is not enabled in a particular phase.

Refactor the setting of priv->emmc_clk so it is a bit clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2024-09-20 09:24:40 +02:00 • committed by Tom Rini
parent e59e50217a
commit b2f571fe71
2 changed files with 6 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
drivers/mmc/rockchip_dw_mmc.c
View file

@ -131,13 +131,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
priv->minmax[1] = dtplat->max_frequency;
ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
if (ret < 0)
return ret;
#else
ret = clk_get_by_index(dev, 1, &priv->clk);
if (ret < 0)
return ret;
#endif
if (ret < 0 && ret != -ENOSYS)
return log_msg_ret("clk", ret);
host->fifo_depth = priv->fifo_depth;
host->fifo_mode = priv->fifo_mode;

9
drivers/mmc/rockchip_sdhci.c
View file

@ -571,20 +571,19 @@ static int rockchip_sdhci_probe(struct udevice *dev)
struct rockchip_sdhc *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
struct sdhci_host *host = &priv->host;
struct clk clk;
struct clk *clk = &priv->emmc_clk;
int ret;
host->max_clk = cfg->f_max;
ret = clk_get_by_index(dev, 0, &clk);
ret = clk_get_by_index(dev, 0, clk);
if (!ret) {
ret = clk_set_rate(&clk, host->max_clk);
ret = clk_set_rate(clk, host->max_clk);
if (IS_ERR_VALUE(ret))
printf("%s clk set rate fail!\n", __func__);
} else {
} else if (ret != -ENOSYS) {
printf("%s fail to get clk\n", __func__);
}
priv->emmc_clk = clk;
priv->dev = dev;
if (data->get_phy) {