Commit graph

854 commits

Author SHA1 Message Date
Tom Rini
ad09ccf7fe Merge patch series "Misc. PowerPC MPC83xx fixes/cleanups"
J. Neuschäfer <j.ne@posteo.net> says:

This patchset contains a few small fixes/cleanups for the MPC83xx
platform.

Link: https://lore.kernel.org/r/20241220-mpc83xx-misc-v2-0-ff4c17ee5fa4@posteo.net
2024-12-30 15:55:33 -06:00
J. Neuschäfer
8803745428 gpio: mpc8xxx: Preserve pre-init state of outputs
The mpc8xxx_gpio driver contains a workaround for certain chips
where the previously written state of outputs cannot be read back
from the GPIO data (GPDAT) register (MPC8572/MPC8536). This workaround
consists of tracking the state of GPDAT in a "shadow register" (i.e. a
software variable). The shadow register is initialized to zero.

This results in a problem w.r.t. outputs that are configured to a
high (1) state before U-Boot runs, but not touched by U-Boot itself:
Due to the zero-initialization, these GPIOs end up being set to zero,
the first time that any other output is set.

To avoid such issues initialize the GPDAT shadow register to the value
previously held by any outputs, if possible. On MPC8572/MPC8536 this
should make no difference, i.e. the shadow register should be
initialized to zero on these chips.

This patch has been tested on a MPC8314E-based board.

Reviewed-by: Sinan Akman <sinan@writeme.com>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-30 15:55:27 -06:00
Jim Liu
787d389350 gpio: npcm: Add persist feature to sgpio module
Base on GPIO hog to support sgpio persist enable feature.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2024-12-30 15:55:01 -06:00
Tom Rini
5cfbf8c364 Prepare v2025.01-rc5
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmdqIAsACgkQFHw5/5Y0
 tyxmdAv/a0dUsibc2oyLJzRFioJO6ib0dro5EHiH1oyF3igOTGe1ifxeQyR/0bb8
 /3Qtr19f77INNjgQmRNpLbBfeoIMm3MeVF+zwQzEvUDEHNNQ0nnxu/yNnJB6Ebej
 xF/vdAP4JoV+KFQXMCMjIyFZcjZh4wGn1L1T8y7GQHS+p1zf0EYA7tPbk5rbwk/E
 xAFSymtWvOZVjLgV9YKp/RqS1+vGHaKydwzUZAncXJzeAMFD2Wm7mnDkd828U/eR
 7vs5BCnRwTgj7iWE6KXJUhFz2hrrBMFTEIV4GNW28vBSCoArlWshLbpKRolEoKY9
 i+dfkBDhghw9fVcTBOSP7BkiFwQl02jPB4Vf8G5ykK11CHO8XTpdjE5buGS1zsiW
 dTX9w4pynCl07p0qYsgGPYf2cE1k6dG6XFNUzH3owyNGiF+66VQeG05V79moQp9F
 ZF0/rux475UhZceXDImdecgkBDsc9gRvu0aX9ZYQtaBCgKJnQ8nyYPXGWZ/u0TSl
 1WVADGUq
 =4mOT
 -----END PGP SIGNATURE-----

Merge tag 'v2025.01-rc5' into next

Prepare v2025.01-rc5
2024-12-25 22:31:04 -06:00
Marek Vasut
4a9c8946b8 gpio: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Peng Fan
4af5084a3b gpio: imx_rgpio2p: Move 8ulp_data to data section
have_dual_base is set to false, so the 8ulp_data will be put in BSS
section which conflicts with the area of u-boot.dtb which padded just
after u-boot-nodtb.bin. So move 8ulp_data to data section to avoid
its content being corrupted by dtb.

Fixes: 51cfa66f2c ("gpio: imx_rgpio2p: support one address")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07 09:07:03 -03:00
Zixun LI
3c69a95b9a dm: gpio: Return error when pull up/down is requested but set_flags ops is not implmentated
Currently in _dm_gpio_set_flags() when set_flags ops is not implemented
direction_output()/_input() is used, but pull up/down is not supported by
these ops.

Signed-off-by: Zixun LI <admin@hifiphile.com>
2024-12-04 14:11:43 -06:00
Zixun LI
94317f881b gpio: at91: Implement ops get_flags
Add ops get_dir_flags() to read status from GPIO registers.

Signed-off-by: Zixun LI <admin@hifiphile.com>
2024-11-29 12:59:27 +02:00
Zixun LI
4c178d4061 gpio: at91: Implement ops set_flags
Support GPIO configuration with following flags:
- in, out, out_active
- open_drain, pull_up

Signed-off-by: Zixun LI <admin@hifiphile.com>
2024-11-29 12:59:27 +02:00
Zixun LI
e4980192b6 gpio: at91: Implement GPIOF_FUNC in get_function()
This patch adds support for determining whether a gpio pin is mapped as
peripheral function.

Signed-off-by: Zixun LI <admin@hifiphile.com>
2024-11-29 12:59:27 +02:00
Neil Armstrong
9b9ccca64c
gpio: qcom_pmic: add again the quirk to skip GPIO configuration on PM8550
The qcom_pmic code is broken for new PMICs and should be fixed,
without the QUIRK the code is broken and the GPIOs don't work
anymore on SM8550 and SM8650 platforms.

Partially revert the revert and only add the quirk on the PM8550
PMIC, making the buttons and MMC detect gpio work again.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Tom Rini
e28e70e392 Merge patch series "Support Aspeed SGPIO controller"
Billy Tsai <billy_tsai@aspeedtech.com> says:

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.

Link: https://lore.kernel.org/r/20241016085955.314236-1-billy_tsai@aspeedtech.com
2024-10-29 16:17:47 -06:00
Billy Tsai
0e53667d4f gpio: Add Aspeed SGPIO driver
The Aspeed SGPIO driver supports the SGPIO controllers found in the
AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down
copy of the upstream Linux kernel driver, adapted for u-boot.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
2024-10-29 12:12:04 -06:00
Maksim Kiselev
370806854e gpio: dw: Add ngpios DT-property support
Starting with Linux commit 7569486d79ae ("gpio: dwapb: Add ngpios
DT-property support") the "snps,nr-gpios" property was marked
as deprecated.

And since all newly added dw-apb-gpio nodes are described using generic
"ngpios" property, it's time to add support for it.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-10-28 16:11:33 +08:00
Philip Balister
3cf94b6f41 mcp230xx_gpio.c: Add a missing include file.
* Fixes a warning about implicit declaration of udelay.

Signed-off-by: Philip Balister <philip@balister.org>
2024-10-24 11:19:31 -06:00
Tom Rini
82686e678e Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Assorted Tegra enhancements. Merged with the recent XPL_BUILD changes,
resolve some whitespace issues and fix the name of the new apalis-tk1
env file by Tom.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-10-13 10:43:24 -06:00
Svyatoslav Ryhel
2ff444d07d drivers: tegra_gpio: add early SPL functions
In some cases access to GPIOs is needed so early that DM
is not ready even nearly. These functions are exactly for
this case.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-10-13 17:20:26 +03:00
Tom Rini
47e544f576 Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"
Simon Glass <sjg@chromium.org> says:

When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL

Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.

For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:

   #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)

In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.

This series starts a change in terminology and usage to resolve the
above issues:

- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
  'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
  defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_

It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.

This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.

The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
2024-10-11 12:23:25 -06:00
Simon Glass
5c10c8badf global: Rename SPL_TPL_ to PHASE_
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:48 -06:00
Simon Glass
c46760d596 global: Rename SPL_ to XPL_
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:48 -06:00
Simon Glass
371dc068bb drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:48 -06:00
Tom Rini
7321b7dd36 Merge tag 'u-boot-imx-next-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22526

- Add DA9063 watchdog support for the imx6q-lxr2 board.
- Add support for DH electronics i.MX8M Plus DHCOM PicoITX
- Add DH i.MX8MP DHCOM SoM on DRC02 carrier board
- Several fsl_esdhc_imx improvements.
- Pas no-mmc-hs400 to mmc2 on imx8mm-cl-iot-gate.
2024-10-05 11:18:16 -06:00
Caleb Connolly
dc554a07ea
Revert "gpio: qcom_pmic: add a quirk to skip GPIO configuration"
This reverts commit 19f000b72b.

The bug in writing was caused by a long-standing error in the SPMI
driver which has since been fixed - c2de620d64 ("spmi: msm: fix
version 5 support"). We can safely enable writing GPIO configuration
now.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-10-04 14:57:03 +02:00
Neil Armstrong
f9bb539460
gpio: msm: add support for special pins
Leverage the data introduced in the struct msm_special_pin_data to allow
setting the gpio direction and value if supported by the pin data.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-10-04 14:57:02 +02:00
Ye Li
dd95eefb3a gpio: adp5585: Add SPL config for ADP5585 driver
So we can disable to build ADP5585 in SPL to save size

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-10-04 09:14:29 -03:00
Tomas Paukrt
75e8b677b7 gpio: mxc_gpio: fix reading state of GPIO pins in output mode
The PSR register works correctly for GPIO pins in input mode,
but always returns 0 for GPIO pins in output mode unless the SION
bit is set.

The DR register should be used for GPIO pins in output mode
to allow correct getting of previously set output value.

Please note that the Linux gpio-mxc driver and the NXP U-Boot mxc_gpio
driver already use the DR register for all GPIO pins in output mode:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=442b2494b17d1a4f0a14721580271eb23ebffd42
4afc3f9094

Signed-off-by: Tomas Paukrt <tomaspaukrt@email.cz>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
2024-08-30 22:32:29 -03:00
Billy Tsai
7c2c235a27 gpio: Add G7 Aspeed gpio controller driver
In the 7th generation of the SoC from Aspeed, the control logic of the
GPIO controller has been updated to support per-pin control. Each pin now
has its own 32-bit register, allowing for individual control of the pin’s
value, direction, interrupt type, and other settings.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
2024-08-27 18:01:38 -06:00
Jim Liu
7c17f02283 gpio: npcm: Add SGPIO support for Nuvoton NPCM SoCs
Add Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver.
BMC can use this driver to increase 64 GPI pins and 64 GPO pins to use.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2024-08-27 14:31:55 -06:00
Marek Vasut
632ba2bd5c drivers: gpio: Remove duplicate newlines
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-07-22 10:53:05 -06:00
Michal Simek
62a3e4016a gpio: Add proper dependency on ZYNQMP_FIRMWARE
ZYNQMP_FIRMWARE can be disabled and driver depends on it that's why record
this dependency via Kconfig.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c3ca38fbb2f4e6948a5ef95b369015de96259709.1717685091.git.michal.simek@amd.com
2024-06-17 16:02:30 +02:00
Michal Simek
40f5046c22 arm64: versal2: Add support for AMD Versal Gen 2
Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2
cpu core each. A lot of IPs are shared with previous families. There are
couple of new IP blocks where the most interesting from user point of view
is UFS.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com
2024-06-17 16:02:29 +02:00
Tom Rini
03de305ec4 Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-20 13:35:03 -06:00
Tom Rini
d678a59d2d Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d, reversing
changes made to 2ee6f3a5f7.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19 08:16:36 -06:00
Tom Rini
6657851f83 gpio: Remove <common.h> and add needed includes
Remove <common.h> from this driver directory and when needed
add missing include files directly.

Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07 08:00:55 -06:00
Caleb Connolly
8bf1eb9a2e
gpio: qcom_pmic: add pm8150l
This is used for the volume keys on some SM8150/SM8250 devices.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23 13:29:28 +02:00
Caleb Connolly
733f6d9820
gpio: qcom_pmic: add pm6125
As with some other modern PMICs, writing to the GPIOs seems to make the
device reset.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23 13:29:27 +02:00
Neil Armstrong
b6f1d33532
gpio: qcom_pmic_gpio: add support for pm8550-gpio
Add support for PM8550 GPIO controller variant, keep read-only
until the GPIO and Pinctrl setup is fixed for new PMICs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23 13:29:02 +02:00
Peng Fan
51cfa66f2c gpio: imx_rgpio2p: support one address
The i.MX8ULP/93 gpio dt-schema have been updated to only have one
address entry, update the driver to support it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-04-15 08:09:26 -03:00
Tom Rini
eff62097f6 Merge tag 'qcom-next-2024Apr04' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
- Ethernet, i2c, and USB support are now enabled by default
- The clock driver gets some bug fixes and cleanup
- Invalid FDTs are now properly detected in board_fdt_blob_setup().
- The pinctrl driver gains preparatory support for per-pin function
  muxes.
- Support is added for two generations of Qualcomm HighSpeed USB PHY
- A power domain driver is added for the Globall Distributed Switch
  Controllers on the GCC hardware block.
- SDM845 gains USB host mode support.
- OF_LIVE is enabled by default for Qualcomm platforms
- Some U-Boot devicetree compatibility fixups are added during init to
  improve compatbility with upstream DT.
2024-04-05 17:23:13 -04:00
Caleb Connolly
4527991563
gpio: msm_gpio: add .set_flags op
The .direction_input and .direction_output ops are deprecated, and don't
seem to behave properly for us. Implement our own .set_flags op to
handle this correctly.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-04 17:46:46 +02:00
Marek Behún
a5505de01d gpio: turris_omnia_mcu: Add support for system power off via sysreset
Add support for system power off via UCLASS_SYSRESET. Newer versions of
Turris Omnia MCU firmware can power off the board (MCU will disable
almost all voltage regulators and go into low power mode).

Move the MCU driver into drivers/misc and register it under UCLASS_MISC.
The sysreset and gpio device are bound as child devices of the MCU device.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-04-04 10:45:27 +02:00
Marek Behún
68e09ae19e gpio: turris_omnia_mcu: Update firmware features reading
Update firmware features reading to try reading 32 bits of features and
fallback to reading 16 bits.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-04-04 10:45:27 +02:00
Marek Behún
c07206fb8b gpio: turris_omnia_mcu: Use byteorder conversion functions
Use byteorder conversion function instead of manually assembling data
from/to MCU.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-04-04 10:45:27 +02:00
Marek Behún
b555148fdd arm: mvebu: turris_omnia: Add header containing MCU command interface and use it
Add header containing all MCU command definitions and use it in board
code and in MCU driver.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-04-04 10:45:27 +02:00
Piotr Wojtaszczyk
3b639f6438 gpio: mcp230xx: Add support for models with SPI interface.
Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
2024-03-20 17:12:51 -04:00
Jonas Karlman
f41738d0f1 gpio: rockchip: Use gpio alias id as gpio bank id
The U-Boot driver try to base the gpio bank id on the gpio-ranges prop
and fall back to base the bank id on the node name. However, the linux
driver try to base the bank id on the gpio alias id and fall back on
node order.

This can cause issues when SoC DT is synced from linux and gpioX@ nodes
has been renamed to gpio@ and gpio-ranges or a SoC specific alias has
not been assigned.

Try to use the gpio alias id as first fallback when a gpio-ranges prop
is missing to ease sync of updated SoC DT. Keep the current fallback on
node name as a third fallback to not affect any existing unsynced DT.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-03-14 11:40:48 +08:00
Quentin Schulz
9f5df9a3ef rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h
The different macros use writel which is defined in asm/io.h, so let's
include the header so users of hardware.h do not need to include
asm/io.h as well.

While at it, remove asm/io.h includes wherever
asm/arch-rockchip/hardware.h is included already.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-03-13 18:15:52 +08:00
Tom Rini
20a0ce574d Prepare v2024.04-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmXvO2YACgkQFHw5/5Y0
 tyxRagwAtLBR/yehfOY5Zw3dKf8kREedas500ueg7nSwV+V2CZO+cwFLrtSVJhXu
 p6dtX0QZxCYidTfaoUOfGLwgvrJoXD/iY6ws8dzVMa9IX2ez3uZDlsPmQG/y2U4i
 rtDn9YgV8oAnLk4hFaaE5vhWfUmtSy6SvJ/foFeQT0B9Er14ep5AII8L/nUcP53w
 FbJ8UVF92i44+zG/0EjpG2pZeftztnVP4YVhU+mbmLLKP49sbrVwFRlo5t+VlB/j
 Q1/RCgxGMPsUG3iNWqIl6rA3VElcZbUm8+YcAy6GqTLOXPxydwBnZVS5UgYapg7y
 Yqu3IMm0LGdXp4klYcdz0tesuFHWan+j227Tme9OLmHgBYBo1WO6zDCITOW1uNVe
 tf3QjIVlrMV4/zglHP/2iceBO1sS49TuzjctCdEBKXb7vZISxgxS7QwmGVVHeigw
 zF4tw0uuzldi+e1yv9rleTIJBN+OuPqUhsyda2Fxq5a2hKW90hv33zzb7ZN5ZvVm
 GlEzhZ6c
 =CqvA
 -----END PGP SIGNATURE-----

Merge tag 'v2024.04-rc4' into next

Prepare v2024.04-rc4
2024-03-11 15:27:20 -04:00
Marek Vasut
f9aabd4579 ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESAS
Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.

Use the following command to perform the rename:

"
$ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Tom Rini
b9f5620a47 Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
- Reworks Qualcomm support to be more generic, dropping board specific
  build targets and relying on DT as the only source of truth
- Switches all Qualcomm devices to use upstream devicetree
2024-03-01 16:32:27 -05:00