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Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next

Browse source 
- Reworks Qualcomm support to be more generic, dropping board specific
  build targets and relying on DT as the only source of truth
- Switches all Qualcomm devices to use upstream devicetree
This commit is contained in:
Tom Rini 2024-03-01 13:54:49 -05:00
commit b9f5620a47
136 changed files with 24039 additions and 2658 deletions
MAINTAINERS
arch
arm
Kconfig
dts
Makefileapq8016-sbc-u-boot.dtsiapq8016-sbc.dtsapq8096-db820c-u-boot.dtsiapq8096-db820c.dtsdragonboard410c-uboot.dtsidragonboard410c.dtsdragonboard820c-uboot.dtsidragonboard820c.dtsdragonboard845c-uboot.dtsidragonboard845c.dtsmsm8916-pm8916.dtsimsm8916.dtsimsm8996.dtsipm8916.dtsipm8994.dtsipm8998.dtsipmi8994.dtsipmi8998.dtsipms405.dtsiqcs404-evb-4000-u-boot.dtsiqcs404-evb-4000.dtsqcs404-evb-uboot.dtsiqcs404-evb.dtsqcs404-evb.dtsiqcs404.dtsisdm845-db845c.dtssdm845-samsung-starqltechn-u-boot.dtsisdm845-samsung-starqltechn.dtssdm845-wcd9340.dtsisdm845.dtsistarqltechn-uboot.dtsistarqltechn.dts
lib
save_prev_bl_data.c
mach-snapdragon
KconfigMakefileboard.cdram.c
include/mach
dram.hgpio.hmisc.h
init_sdm845.cmisc.csysmap-apq8016.csysmap-apq8096.csysmap-qcs404.csysmap-sdm845.c
sandbox/dts
sandbox.dtsi
board/qualcomm
dragonboard410c
KconfigMakefile
configs
chainloaded.config
dragonboard410c.c
dragonboard820c
KconfigMakefiledragonboard820c.chead.Su-boot.lds
dragonboard845c
Kconfig
qcs404-evb
KconfigMakefileqcs404-evb.c
configs
dragonboard410c_defconfigdragonboard820c_defconfigdragonboard845c_defconfigqcom_defconfigqcs404evb_defconfigstarqltechn_defconfig
doc
board/qualcomm
board.rstdebugging.rstdragonboard410c.rstindex.rstqcs404.rstsdm845.rst
device-tree-bindings
mmc
msm_sdhci.txt
usb
ehci-msm.txt
drivers
clk/qcom
clock-apq8016.cclock-apq8096.cclock-qcs404.c
gpio
msm_gpio.cqcom_pmic_gpio.c
mmc
msm_sdhci.c
phy/qcom
msm8916-usbh-phy.c
pinctrl/qcom
pinctrl-apq8016.cpinctrl-apq8096.cpinctrl-ipq4019.cpinctrl-qcom.cpinctrl-qcs404.cpinctrl-sdm845.c
serial
Kconfigserial_msm.c
usb
dwc3
dwc3-generic.c
host
ehci-msm.c
include
configs
dragonboard845c.hqcom.hqcs404-evb.hsdm845.h
dt-bindings
arm
coresight-cti-dt.h
clock
qcom,camcc-sdm845.h
Show more

12
MAINTAINERS
View file

@ -603,18 +603,22 @@ M: Caleb Connolly <caleb.connolly@linaro.org>
M: Neil Armstrong <neil.armstrong@linaro.org>
R: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: arch/arm/mach-snapdragon/
F: drivers/button/button-qcom-pmic.c
F: drivers/clk/qcom/
F: arch/arm/dts/msm8*.dtsi
F: arch/arm/dts/pm8???.dtsi
F: arch/arm/dts/pms405.dtsi
F: arch/arm/dts/sdm845.dtsi
F: drivers/*/*/pm8???-*
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
F: drivers/phy/msm8916-usbh-phy.c
F: drivers/pinctrl/qcom/
F: drivers/serial/serial_msm.c
F: drivers/serial/serial_msm_geni.c
F: drivers/smem/msm_smem.c
F: drivers/spmi/spmi-msm.c
F: drivers/usb/host/ehci-msm.c
N: qcom
N: snapdragon
N: qualcomm
ARM STI
M: Patrice Chotard <patrice.chotard@foss.st.com>

4
arch/arm/Kconfig
View file

@ -1096,6 +1096,10 @@ config ARCH_SNAPDRAGON
select OF_SEPARATE
select SMEM
select SPMI
select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
select LINUX_KERNEL_IMAGE_HEADER
imply CMD_DM
config ARCH_SOCFPGA

9
arch/arm/dts/Makefile
View file

@ -624,10 +624,11 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
apq8096-db820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
qcs404-evb-4000.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb

20
arch/arm/dts/apq8016-sbc-u-boot.dtsi Normal file
View file

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024, Linaro Ltd.
*/
/ {
/* When running as a first-stage bootloader this isn't filled in automatically */
memory@80000000 {
reg = <0 0x80000000 0 0x3da00000>;
};
};
/*
* When running as a first-stage bootloader, we need to re-configure the UART pins
* because SBL de-initialises them. Indicate that the UART pins should be configured
* during all boot stages.
*/
&blsp_uart2_default {
bootph-all;
};

729
arch/arm/dts/apq8016-sbc.dts Normal file
View file

@ -0,0 +1,729 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
#include <dt-bindings/sound/apq8016-lpass.h>
/ {
model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
compatible = "qcom,apq8016-sbc", "qcom,apq8016";
aliases {
mmc0 = &sdhc_1; /* eMMC */
mmc1 = &sdhc_2; /* SD card */
serial0 = &blsp_uart2;
serial1 = &blsp_uart1;
usid0 = &pm8916_0;
i2c0 = &blsp_i2c2;
i2c1 = &blsp_i2c6;
i2c3 = &blsp_i2c4;
spi0 = &blsp_spi5;
spi1 = &blsp_spi3;
};
chosen {
stdout-path = "serial0";
};
reserved-memory {
ramoops@bff00000 {
compatible = "ramoops";
reg = <0x0 0xbff00000 0x0 0x100000>;
record-size = <0x20000>;
console-size = <0x20000>;
ftrace-size = <0x20000>;
};
};
usb2513 {
compatible = "smsc,usb3503";
reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7533_out>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&msm_key_volp_n_default>;
button {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
};
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&tlmm_leds>,
<&pm8916_gpios_leds>,
<&pm8916_mpps_leds>;
compatible = "gpio-leds";
led@1 {
label = "apq8016-sbc:green:user1";
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led@2 {
label = "apq8016-sbc:green:user2";
function = LED_FUNCTION_DISK_ACTIVITY;
color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led@3 {
label = "apq8016-sbc:green:user3";
function = LED_FUNCTION_DISK_ACTIVITY;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";
};
led@4 {
label = "apq8016-sbc:green:user4";
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
panic-indicator;
default-state = "off";
};
led@5 {
label = "apq8016-sbc:yellow:wlan";
function = LED_FUNCTION_WLAN;
color = <LED_COLOR_ID_YELLOW>;
gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
led@6 {
label = "apq8016-sbc:blue:bt";
function = LED_FUNCTION_BLUETOOTH;
color = <LED_COLOR_ID_BLUE>;
gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "bluetooth-power";
default-state = "off";
};
};
};
&blsp_i2c2 {
/* On Low speed expansion: LS-I2C0 */
status = "okay";
};
&blsp_i2c4 {
/* On High speed expansion: HS-I2C2 */
status = "okay";
adv_bridge: bridge@39 {
status = "okay";
compatible = "adi,adv7533";
reg = <0x39>;
interrupt-parent = <&tlmm>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
clocks = <&rpmcc RPM_SMD_BB_CLK2>;
clock-names = "cec";
pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
avdd-supply = <&pm8916_l6>;
a2vdd-supply = <&pm8916_l6>;
dvdd-supply = <&pm8916_l6>;
pvdd-supply = <&pm8916_l6>;
v1p2-supply = <&pm8916_l6>;
v3p3-supply = <&pm8916_l17>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
#sound-dai-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7533_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
port@1 {
reg = <1>;
adv7533_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&blsp_i2c6 {
/* On Low speed expansion: LS-I2C1 */
status = "okay";
};
&blsp_spi3 {
/* On High speed expansion: HS-SPI1 */
status = "okay";
};
&blsp_spi5 {
/* On Low speed expansion: LS-SPI0 */
status = "okay";
};
&blsp_uart1 {
status = "okay";
label = "LS-UART0";
};
&blsp_uart2 {
status = "okay";
label = "LS-UART1";
};
&camss {
status = "okay";
};
&gpu {
status = "okay";
};
&lpass {
status = "okay";
};
&lpass_codec {
status = "okay";
};
&mba_mem {
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dsi0_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&adv7533_in>;
};
&mpss {
status = "okay";
firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn";
};
&mpss_mem {
status = "okay";
reg = <0x0 0x86800000 0x0 0x2b00000>;
};
&pm8916_codec {
status = "okay";
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&pm8916_rpm_regulators {
/*
* The 96Boards specification expects a 1.8V power rail on the low-speed
* expansion connector that is able to provide at least 0.18W / 100 mA.
* L15/L16 are connected in parallel to provide 55 mA each. A minimum load
* must be specified to ensure the regulators are not put in LPM where they
* would only provide 5 mA.
*/
pm8916_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-system-load = <50000>;
regulator-allow-set-load;
regulator-always-on;
};
pm8916_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-system-load = <50000>;
regulator-allow-set-load;
regulator-always-on;
};
pm8916_l17: l17 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&sdhc_1 {
status = "okay";
};
&sdhc_2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&sound {
status = "okay";
pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
pinctrl-names = "default", "sleep";
model = "DB410c";
audio-routing =
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
quaternary-dai-link {
link-name = "ADV7533";
cpu {
sound-dai = <&lpass MI2S_QUATERNARY>;
};
codec {
sound-dai = <&adv_bridge 0>;
};
};
primary-dai-link {
link-name = "WCD";
cpu {
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>;
};
};
tertiary-dai-link {
link-name = "WCD-Capture";
cpu {
sound-dai = <&lpass MI2S_TERTIARY>;
};
codec {
sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>;
};
};
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
pinctrl-names = "default", "device";
pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
};
&usb_hs_phy {
extcon = <&usb_id>;
};
&venus {
status = "okay";
};
&venus_mem {
status = "okay";
};
&wcnss {
status = "okay";
firmware-name = "qcom/apq8016/wcnss.mbn";
};
&wcnss_ctrl {
firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&wcnss_mem {
status = "okay";
};
/* Enable CoreSight */
&cti0 { status = "okay"; };
&cti1 { status = "okay"; };
&cti12 { status = "okay"; };
&cti13 { status = "okay"; };
&cti14 { status = "okay"; };
&cti15 { status = "okay"; };
&debug0 { status = "okay"; };
&debug1 { status = "okay"; };
&debug2 { status = "okay"; };
&debug3 { status = "okay"; };
&etf { status = "okay"; };
&etm0 { status = "okay"; };
&etm1 { status = "okay"; };
&etm2 { status = "okay"; };
&etm3 { status = "okay"; };
&etr { status = "okay"; };
&funnel0 { status = "okay"; };
&funnel1 { status = "okay"; };
&replicator { status = "okay"; };
&stm { status = "okay"; };
&tpiu { status = "okay"; };
/*
* 2mA drive strength is not enough when connecting multiple
* I2C devices with different pull up resistors.
*/
&blsp_i2c2_default {
drive-strength = <16>;
};
&blsp_i2c4_default {
drive-strength = <16>;
};
&blsp_i2c6_default {
drive-strength = <16>;
};
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from the schematic "DragonBoard410c"
* dated monday, august 31, 2015. Page 5 in particular.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART3. This is only for the informational lines i.e. "[FOO]",
* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
* ones actually used for GPIO.
*/
&tlmm {
gpio-line-names =
"[UART0_TX]", /* GPIO_0, LSEC pin 5 */
"[UART0_RX]", /* GPIO_1, LSEC pin 7 */
"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */
"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */
"[UART1_TX]", /* GPIO_4, LSEC pin 11 */
"[UART1_RX]", /* GPIO_5, LSEC pin 13 */
"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */
"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */
"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */
"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */
"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */
"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */
"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */
"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */
"[I2C3_SDA]", /* HSEC pin 38 */
"[I2C3_SCL]", /* HSEC pin 36 */
"[SPI0_MOSI]", /* LSEC pin 14 */
"[SPI0_MISO]", /* LSEC pin 10 */
"[SPI0_CS_N]", /* LSEC pin 12 */
"[SPI0_CLK]", /* LSEC pin 8 */
"HDMI_HPD_N", /* GPIO 20 */
"USR_LED_1_CTRL",
"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */
"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */
"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */
"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */
"[CSI0_MCLK]", /* HSEC pin 15 */
"[CSI1_MCLK]", /* HSEC pin 17 */
"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */
"[I2C2_SDA]", /* HSEC pin 34 */
"[I2C2_SCL]", /* HSEC pin 32 */
"DSI2HDMI_INT_N",
"DSI_SW_SEL_APQ",
"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */
"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */
"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */
"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */
"FORCED_USB_BOOT",
"SD_CARD_DET_N",
"[WCSS_BT_SSBI]",
"[WCSS_WLAN_DATA_2]", /* GPIO 40 */
"[WCSS_WLAN_DATA_1]",
"[WCSS_WLAN_DATA_0]",
"[WCSS_WLAN_SET]",
"[WCSS_WLAN_CLK]",
"[WCSS_FM_SSBI]",
"[WCSS_FM_SDI]",
"[WCSS_BT_DAT_CTL]",
"[WCSS_BT_DAT_STB]",
"NC",
"NC", /* GPIO 50 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC", /* GPIO 60 */
"NC",
"NC",
"[CDC_PDM0_CLK]",
"[CDC_PDM0_SYNC]",
"[CDC_PDM0_TX0]",
"[CDC_PDM0_RX0]",
"[CDC_PDM0_RX1]",
"[CDC_PDM0_RX2]",
"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */
"NC", /* GPIO 70 */
"NC",
"NC",
"NC",
"NC", /* GPIO 74 */
"NC",
"NC",
"NC",
"NC",
"NC",
"BOOT_CONFIG_0", /* GPIO 80 */
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_3",
"NC",
"NC",
"BOOT_CONFIG_5",
"NC",
"NC",
"NC",
"NC", /* GPIO 90 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC", /* GPIO 100 */
"NC",
"NC",
"NC",
"SSBI_GPS",
"NC",
"NC",
"KEY_VOLP_N",
"NC",
"NC",
"[LS_EXP_MI2S_WS]", /* GPIO 110 */
"NC",
"NC",
"[LS_EXP_MI2S_SCK]",
"[LS_EXP_MI2S_DATA0]",
"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */
"NC",
"[DSI2HDMI_MI2S_WS]",
"[DSI2HDMI_MI2S_SCK]",
"[DSI2HDMI_MI2S_DATA0]",
"USR_LED_2_CTRL", /* GPIO 120 */
"SB_HS_ID";
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tlmm_leds: tlmm-leds-state {
pins = "gpio21", "gpio120";
function = "gpio";
output-low;
};
usb_id_default: usb-id-default-state {
pins = "gpio121";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
adv7533_int_active: adv533-int-active-state {
pins = "gpio31";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
adv7533_int_suspend: adv7533-int-suspend-state {
pins = "gpio31";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
adv7533_switch_active: adv7533-switch-active-state {
pins = "gpio32";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
adv7533_switch_suspend: adv7533-switch-suspend-state {
pins = "gpio32";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
msm_key_volp_n_default: msm-key-volp-n-default-state {
pins = "gpio107";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&pm8916_gpios {
gpio-line-names =
"USR_LED_3_CTRL",
"USR_LED_4_CTRL",
"USB_HUB_RESET_N_PM",
"USB_SW_SEL_PM";
usb_hub_reset_pm: usb-hub-reset-pm-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
input-disable;
output-high;
};
usb_hub_reset_pm_device: usb-hub-reset-pm-device-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
usb_sw_sel_pm: usb-sw-sel-pm-state {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
output-high;
};
usb_sw_sel_pm_device: usb-sw-sel-pm-device-state {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
output-low;
};
pm8916_gpios_leds: pm8916-gpios-leds-state {
pins = "gpio1", "gpio2";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
};
&pm8916_mpps {
gpio-line-names =
"VDD_PX_BIAS",
"WLAN_LED_CTRL",
"BT_LED_CTRL",
"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */
pinctrl-names = "default";
pinctrl-0 = <&ls_exp_gpio_f>;
ls_exp_gpio_f: pm8916-mpp4-state {
pins = "mpp4";
function = "digital";
output-low;
power-source = <PM8916_MPP_L5>; /* 1.8V */
};
pm8916_mpps_leds: pm8916-mpps-state {
pins = "mpp2", "mpp3";
function = "digital";
output-low;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024, Linaro Ltd.
*/
/ {
/* Ensure that the fdtfile variable is generated properly */
compatible = "qcom,apq8096-db820c", "qcom,apq8096";
};
&sdhc2 {
status = "okay";
clock-frequency = <100000000>;
};

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arch/arm/dts/dragonboard410c-uboot.dtsi
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// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Dragonboard 410c pins
*
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
/ {
smem {
bootph-all;
};
soc {
bootph-all;
pinctrl@1000000 {
bootph-all;
uart {
bootph-all;
};
};
qcom,gcc@1800000 {
bootph-all;
};
serial@78b0000 {
bootph-all;
};
};
};
&pm8916_gpios {
usb_hub_reset_pm {
gpios = <&pm8916_gpios 2 0>;
};
usb_sw_sel_pm {
gpios = <&pm8916_gpios 3 0>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm APQ8016 based Dragonboard 410C board device tree source
*
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Dragonboard 410c";
compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
qcom,board-id = <0x10018 0x0>;
#address-cells = <0x2>;
#size-cells = <0x2>;
aliases {
usb0 = "/soc/ehci@78d9000";
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x3da00000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@86300000 {
reg = <0x0 0x86300000 0x0 0x100000>;
no-map;
};
};
chosen {
stdout-path = "/soc/serial@78b0000";
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
rpm_msg_ram: memory@60000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x60000 0x8000>;
};
soc_gpios: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x1000000 0x400000>;
gpio-controller;
gpio-count = <122>;
gpio-bank-name="soc";
#gpio-cells = <2>;
blsp1_uart: uart {
function = "blsp1_uart";
pins = "GPIO_4", "GPIO_5";
drive-strength = <8>;
bias-disable;
};
};
clkc: qcom,gcc@1800000 {
compatible = "qcom,gcc-apq8016";
reg = <0x1800000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b0000 0x200>;
clock = <&clkc 4>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp1_uart>;
};
ehci@78d9000 {
compatible = "qcom,ehci-host";
reg = <0x78d9000 0x400>;
phys = <&ehci_phy>;
};
ehci_phy: ehci_phy@78d9000 {
compatible = "qcom,apq8016-usbphy";
reg = <0x78d9000 0x400>;
#phy-cells = <0>;
};
sdhci@07824000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c 0x7824000 0x800>;
bus-width = <0x8>;
index = <0x0>;
non-removable;
clock = <&clkc 0>;
clock-frequency = <100000000>;
};
sdhci@07864000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7864900 0x11c 0x7864000 0x800>;
index = <0x1>;
bus-width = <0x4>;
clock = <&clkc 1>;
clock-frequency = <200000000>;
cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>;
};
wcnss {
bt {
compatible="qcom,wcnss-bt";
};
wifi {
compatible="qcom,wcnss-wlan";
};
};
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
<0x02400000 0x400000>,
<0x02c00000 0x400000>,
<0x03800000 0x200000>,
<0x0200a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
#address-cells = <0x1>;
#size-cells = <0x1>;
pmic0: pm8916@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800 0x100>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
debounce = <15625>;
bias-pull-up;
};
pm8916_resin: resin {
compatible = "qcom,pm8941-resin";
debounce = <15625>;
bias-pull-up;
};
};
pm8916_gpios: pm8916_gpios@c000 {
compatible = "qcom,pm8916-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-ranges = <&pm8916_gpios 0 0 4>;
#gpio-cells = <2>;
};
};
pmic1: pm8916@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 0x1>;
};
};
};
leds {
compatible = "gpio-leds";
user1 {
label = "green:user1";
gpios = <&soc_gpios 21 0>;
};
user2 {
label = "green:user2";
gpios = <&soc_gpios 120 0>;
};
user3 {
label = "green:user3";
gpios = <&pm8916_gpios 0 0>;
};
user4 {
label = "green:user4";
gpios = <&pm8916_gpios 1 0>;
};
};
};
#include "dragonboard410c-uboot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Dragonboard 820c pins
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
/ {
smem {
bootph-all;
};
soc {
bootph-all;
pinctrl@1010000 {
bootph-all;
uart {
bootph-all;
};
};
clock-controller@300000 {
bootph-all;
};
serial@75b0000 {
bootph-all;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm APQ8096 based Dragonboard 820C board device tree source
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
/dts-v1/;
#include "skeleton64.dtsi"
/ {
model = "Qualcomm Technologies, Inc. DB820c";
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &blsp2_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@86300000 {
reg = <0x0 0x86300000 0x0 0x200000>;
no-map;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x300000 0x90000>;
};
pinctrl: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x1010000 0x400000>;
blsp8_uart: uart {
function = "blsp_uart8";
pins = "GPIO_4", "GPIO_5";
drive-strength = <8>;
bias-disable;
};
};
blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
clock = <&gcc 4>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp8_uart>;
};
sdhc2: sdhci@74a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
index = <0x0>;
bus-width = <4>;
clock = <&gcc 0>;
clock-frequency = <200000000>;
};
spmi_bus: spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0400f000 0x1000>,
<0x04400000 0x800000>,
<0x04c00000 0x800000>,
<0x05800000 0x200000>,
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
#address-cells = <0x1>;
#size-cells = <0x1>;
pmic0: pm8994@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800 0x100>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
debounce = <15625>;
bias-pull-up;
};
pm8994_resin: resin {
compatible = "qcom,pm8941-resin";
debounce = <15625>;
bias-pull-up;
};
};
pm8994_gpios: pm8994_gpios@c000 {
compatible = "qcom,pm8994-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-ranges = <&pm8994_gpios 0 0 22>;
#gpio-cells = <2>;
};
};
pmic1: pm8994@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
};
};
#include "dragonboard820c-uboot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
* (dragonboard845c) pins
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/
{
soc {
bootph-all;
serial@a84000 {
bootph-all;
};
clock-controller@100000 {
bootph-all;
};
pinctrl@3400000 {
bootph-all;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm Robotics RB3 Development (dragonboard845c) board device
* tree source
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/dts-v1/;
#include "sdm845.dtsi"
/ {
model = "Thundercomm Dragonboard 845c";
compatible = "thundercomm,db845c", "qcom,sdm845";
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart9;
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xfdfa0000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc: soc {
serial@a84000 {
status = "okay";
};
};
};
&pm8998_resin {
status = "okay";
};
#include "dragonboard845c-uboot.dtsi"

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// SPDX-License-Identifier: GPL-2.0-only
/*
* msm8916-pm8916.dtsi describes common properties (e.g. regulator connections)
* that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC.
* Many regulators have a fixed purpose in the original reference design and
* were rarely re-used for different purposes. Devices that deviate from the
* typical reference design should not make use of this include and instead add
* the necessary properties in the board-specific device tree.
*/
#include "msm8916.dtsi"
#include "pm8916.dtsi"
&camss {
vdda-supply = <&pm8916_l2>;
};
&mdss_dsi0 {
vdda-supply = <&pm8916_l2>;
vddio-supply = <&pm8916_l6>;
};
&mdss_dsi0_phy {
vddio-supply = <&pm8916_l6>;
};
&mpss {
pll-supply = <&pm8916_l7>;
};
&pm8916_codec {
vdd-cdc-io-supply = <&pm8916_l5>;
vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
vdd-micbias-supply = <&pm8916_l13>;
};
&sdhc_1 {
vmmc-supply = <&pm8916_l8>;
vqmmc-supply = <&pm8916_l5>;
};
&sdhc_2 {
vmmc-supply = <&pm8916_l11>;
vqmmc-supply = <&pm8916_l12>;
};
&usb_hs_phy {
v1p8-supply = <&pm8916_l7>;
v3p3-supply = <&pm8916_l13>;
};
&wcnss {
vddpx-supply = <&pm8916_l7>;
};
&wcnss_iris {
vddxo-supply = <&pm8916_l7>;
vddrfa-supply = <&pm8916_s3>;
vddpa-supply = <&pm8916_l9>;
vdddig-supply = <&pm8916_l5>;
};
&rpm_requests {
pm8916_rpm_regulators: regulators {
compatible = "qcom,rpm-pm8916-regulators";
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>;
/* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
pm8916_s3: s3 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on; /* Needed for L2 */
};
pm8916_s4: s4 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <2150000>;
regulator-always-on; /* Needed for L5/L7 */
};
/*
* Some of the regulators are unused or managed by another
* processor (e.g. the modem). We should still define nodes for
* them to ensure the vote from the application processor can be
* dropped in case the regulators are already on during boot.
*
* The labels for these nodes are omitted on purpose because
* boards should configure a proper voltage before using them.
*/
l1 {};
pm8916_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on; /* Needed for LPDDR RAM */
};
/* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
l4 {};
pm8916_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on; /* Needed for most digital I/O */
};
pm8916_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8916_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on; /* Needed for CPU PLL */
};
pm8916_l8: l8 {
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
};
pm8916_l9: l9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l10 {};
pm8916_l11: l11 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
pm8916_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8916_l13: l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l14 {};
l15 {};
l16 {};
l17 {};
l18 {};
};
};

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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pm8916_0: pmic@0 {
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8916_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
watchdog {
compatible = "qcom,pm8916-wdt";
interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
timeout-sec = <60>;
};
};
pm8916_usbin: usb-detect@1300 {
compatible = "qcom,pm8941-misc";
reg = <0x1300>;
interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_vbus";
status = "disabled";
};
pm8916_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8916_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <VADC_USBIN>;
qcom,pre-scaling = <1 10>;
};
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 3>;
};
channel@8 {
reg = <VADC_DIE_TEMP>;
};
channel@9 {
reg = <VADC_REF_625MV>;
};
channel@a {
reg = <VADC_REF_1250MV>;
};
channel@e {
reg = <VADC_GND_REF>;
};
channel@f {
reg = <VADC_VDD_VADC>;
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm8916_mpps: mpps@a000 {
compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pm8916_mpps 0 0 4>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8916_gpios: gpio@c000 {
compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8916_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8916_1: pmic@1 {
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8916_pwm: pwm {
compatible = "qcom,pm8916-pwm";
#pwm-cells = <2>;
status = "disabled";
};
pm8916_vib: vibrator@c000 {
compatible = "qcom,pm8916-vib";
reg = <0xc000>;
status = "disabled";
};
pm8916_codec: audio-codec@f000 {
compatible = "qcom,pm8916-wcd-analog-codec";
reg = <0xf000>;
interrupt-parent = <&spmi_bus>;
interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
<0x1 0xf0 0x1 IRQ_TYPE_NONE>,
<0x1 0xf0 0x2 IRQ_TYPE_NONE>,
<0x1 0xf0 0x3 IRQ_TYPE_NONE>,
<0x1 0xf0 0x4 IRQ_TYPE_NONE>,
<0x1 0xf0 0x5 IRQ_TYPE_NONE>,
<0x1 0xf0 0x6 IRQ_TYPE_NONE>,
<0x1 0xf0 0x7 IRQ_TYPE_NONE>,
<0x1 0xf1 0x0 IRQ_TYPE_NONE>,
<0x1 0xf1 0x1 IRQ_TYPE_NONE>,
<0x1 0xf1 0x2 IRQ_TYPE_NONE>,
<0x1 0xf1 0x3 IRQ_TYPE_NONE>,
<0x1 0xf1 0x4 IRQ_TYPE_NONE>,
<0x1 0xf1 0x5 IRQ_TYPE_NONE>;
interrupt-names = "cdc_spk_cnp_int",
"cdc_spk_clip_int",
"cdc_spk_ocp_int",
"mbhc_ins_rem_det1",
"mbhc_but_rel_det",
"mbhc_but_press_det",
"mbhc_ins_rem_det",
"mbhc_switch_int",
"cdc_ear_ocp_int",
"cdc_hphr_ocp_int",
"cdc_hphl_ocp_det",
"cdc_ear_cnp_int",
"cdc_hphr_cnp_int",
"cdc_hphl_cnp_int";
#sound-dai-cells = <1>;
status = "disabled";
};
};
};

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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8994-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pm8994_temp>;
trips {
pm8994_alert0: pm8994-alert0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
pm8994_crit: pm8994-crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmic@0 {
compatible = "qcom,pm8994", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8994_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
pm8994_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8994_vadc VADC_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8994_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
channel@8 {
reg = <VADC_DIE_TEMP>;
label = "die_temp";
};
channel@9 {
reg = <VADC_REF_625MV>;
label = "ref_625mv";
};
channel@a {
reg = <VADC_REF_1250MV>;
label = "ref_1250mv";
};
channel@e {
reg = <VADC_GND_REF>;
};
channel@f {
reg = <VADC_VDD_VADC>;
};
};
pm8994_gpios: gpio@c000 {
compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8994_gpios 0 0 22>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8994_mpps: mpps@a000 {
compatible = "qcom,pm8994-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pm8994_mpps 0 0 8>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@1 {
compatible = "qcom,pm8994", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8994_lpg: pwm {
compatible = "qcom,pm8994-lpg";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
pm8994_spmi_regulators: regulators {
compatible = "qcom,pm8994-regulators";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright 2018 Google LLC. */
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
/ {
thermal-zones {
pm8998-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pm8998_temp>;
trips {
pm8998_alert0: pm8998-alert0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
pm8998_crit: pm8998-crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm8998_lsid0: pmic@0 {
compatible = "qcom,pm8998", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8998_pon: pon@800 {
compatible = "qcom,pm8998-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pm8998_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8998_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
pm8998_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8998_coincell: charger@2800 {
compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell";
reg = <0x2800>;
status = "disabled";
};
pm8998_adc: adc@3100 {
compatible = "qcom,spmi-adc-rev2";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@6 {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
};
};
pm8998_adc_tm: adc-tm@3400 {
compatible = "qcom,spmi-adc-tm-hc";
reg = <0x3400>;
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm8998_gpios: gpio@c000 {
compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8998_gpios 0 0 26>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8998_lsid1: pmic@1 {
compatible = "qcom,pm8998", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};

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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@2 {
compatible = "qcom,pmi8994", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8994_gpios: gpio@c000 {
compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pmi8994_gpios 0 0 10>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmi8994_mpps: mpps@a000 {
compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
gpio-ranges = <&pmi8994_mpps 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@3 {
compatible = "qcom,pmi8994", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8994_lpg: pwm {
compatible = "qcom,pmi8994-lpg";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
pmi8994_spmi_regulators: regulators {
compatible = "qcom,pmi8994-regulators";
};
pmi8994_wled: wled@d800 {
compatible = "qcom,pmi8994-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
qcom,cabc;
qcom,external-pfet;
status = "disabled";
};
};
};

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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmi8998_lsid0: pmic@2 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8998_charger: charger@1000 {
compatible = "qcom,pmi8998-charger";
reg = <0x1000>;
interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usb-plugin",
"bat-ov",
"wdog-bark",
"usbin-icl-change";
io-channels = <&pmi8998_rradc 3>,
<&pmi8998_rradc 4>;
io-channel-names = "usbin_i", "usbin_v";
status = "disabled";
};
pmi8998_gpios: gpio@c000 {
compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pmi8998_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmi8998_rradc: adc@4500 {
compatible = "qcom,pmi8998-rradc";
reg = <0x4500>;
#io-channel-cells = <1>;
};
};
pmi8998_lsid1: pmic@3 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
labibb {
compatible = "qcom,pmi8998-lab-ibb";
ibb: ibb {
interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
<0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sc-err", "ocp";
};
lab: lab {
interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sc-err", "ocp";
};
};
pmi8998_lpg: pwm {
compatible = "qcom,pmi8998-lpg";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
pmi8998_flash: led-controller@d300 {
compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led";
reg = <0xd300>;
status = "disabled";
};
pmi8998_wled: leds@d800 {
compatible = "qcom,pmi8998-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, Linaro Limited
*/
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
thermal-zones {
pms405-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pms405_temp>;
trips {
pms405_alert0: pms405-alert0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
pms405_crit: pms405-crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pms405_0: pms405@0 {
compatible = "qcom,pms405", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pms405_gpios: gpio@c000 {
compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pms405_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pon@800 {
compatible = "qcom,pms405-pon";
reg = <0x0800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
};
pms405_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pms405_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pms405_adc: adc@3100 {
compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
channel@131 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
channel@77 {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm1";
};
channel@79 {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm3";
};
channel@76 {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "xo_therm";
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
};
};
pms405_1: pms405@1 {
compatible = "qcom,pms405", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
pms405_spmi_regulators: regulators {
compatible = "qcom,pms405-regulators";
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/gpio/gpio.h>
/delete-node/ &usb3_vbus_reg;
/delete-node/ &usb_vbus_boost_pin;
/ {
/* U-Boot uses different bindings for GPIO regulators, this
* one is required for USB
*/
usb3_vbus_reg: usb3_vbus_reg {
compatible = "regulator-gpio";
regulator-name = "usb3_vbus_reg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-gpios = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
states = <0 0>, <5000000 1>;
};
};
&blsp1_uart2 {
/* This defines the bit clock divider which defines the baud rate.
* 0xFF is a divider of 16 for both the RX and TX lines. The QCS404
* clock driver in U-Boot hardcodes a 1843200Hz frequency for the
* UART core clock, and 1843200 / 16 = 115200.
*/
bit-rate = <0xFF>;
};
&gcc {
/* The clock framework in U-Boot "sort of" has the idea of linking an
* individual clock to a device via uclass_priv. However the qcom clock
* driver instead associates many clocks with a single device. This is
* usually fine but it seems that assigned-clocks wreak havoc on this
* and we wind up having a reference to the XO clock which is associated
* with the qcom_clk device...
* For now we'll just remove these properties, no other board has these.
*/
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clocks;
};
&usb3_dwc3 {
/* Make sure the VBUS supply is switched on */
vbus-supply = <&usb3_vbus_reg>;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "qcs404-evb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
"qcom,qcs404";
};
&ethernet {
status = "okay";
snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet_defaults>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
reg = <0x4>;
};
};
};
&tlmm {
ethernet_defaults: ethernet-defaults-state {
int-pins {
pins = "gpio61";
function = "rgmii_int";
bias-disable;
drive-strength = <2>;
};
mdc-pins {
pins = "gpio76";
function = "rgmii_mdc";
bias-pull-up;
};
mdio-pins {
pins = "gpio75";
function = "rgmii_mdio";
bias-pull-up;
};
tx-pins {
pins = "gpio67", "gpio66", "gpio65", "gpio64";
function = "rgmii_tx";
bias-pull-up;
drive-strength = <16>;
};
rx-pins {
pins = "gpio73", "gpio72", "gpio71", "gpio70";
function = "rgmii_rx";
bias-disable;
drive-strength = <2>;
};
tx-ctl-pins {
pins = "gpio68";
function = "rgmii_ctl";
bias-pull-up;
drive-strength = <16>;
};
rx-ctl-pins {
pins = "gpio74";
function = "rgmii_ctl";
bias-disable;
drive-strength = <2>;
};
tx-ck-pins {
pins = "gpio63";
function = "rgmii_ck";
bias-pull-up;
drive-strength = <16>;
};
rx-ck-pins {
pins = "gpio69";
function = "rgmii_ck";
bias-disable;
drive-strength = <2>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle QCS404 EVB pre-relocation devices
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/ {
soc {
bootph-all;
pinctrl_north@1300000 {
bootph-all;
};
clock-controller@1800000 {
bootph-all;
};
serial@78b1000 {
bootph-all;
};
};
};
&pms405_gpios {
usb_vbus_boost_pin {
gpios = <&pms405_gpios 2 0>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm QCS404 based evaluation board device tree source
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
/ {
model = "Qualcomm Technologies, Inc. QCS404 EVB";
compatible = "qcom,qcs404-evb", "qcom,qcs404";
#address-cells = <0x2>;
#size-cells = <0x2>;
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &debug_uart;
i2c0 = &blsp1_i2c0;
i2c1 = &blsp1_i2c1;
i2c2 = &blsp1_i2c2;
i2c3 = &blsp1_i2c3;
i2c4 = &blsp1_i2c4;
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
soc_gpios: pinctrl_north@1300000 {
compatible = "qcom,qcs404-pinctrl";
reg = <0x1300000 0x200000>;
gpio-controller;
gpio-count = <120>;
gpio-bank-name="soc";
#gpio-cells = <2>;
blsp1_uart2: uart {
pins = "GPIO_17", "GPIO_18";
function = "blsp_uart2";
};
blsp1_i2c0_default: blsp1-i2c0-default {
pins = "GPIO_32", "GPIO_33";
function = "blsp_i2c0";
};
blsp1_i2c1_default: blsp1-i2c1-default {
pins = "GPIO_24", "GPIO_25";
function = "blsp_i2c1";
};
blsp1_i2c2_default: blsp1-i2c2-default {
sda {
pins = "GPIO_19";
function = "blsp_i2c_sda_a2";
};
scl {
pins = "GPIO_20";
function = "blsp_i2c_scl_a2";
};
};
blsp1_i2c3_default: blsp1-i2c3-default {
pins = "GPIO_84", "GPIO_85";
function = "blsp_i2c3";
};
blsp1_i2c4_default: blsp1-i2c4-default {
pins = "GPIO_117", "GPIO_118";
function = "blsp_i2c4";
};
ethernet_defaults: ethernet-defaults {
int {
pins = "GPIO_61";
function = "rgmii_int";
bias-disable;
drive-strength = <2>;
};
mdc {
pins = "GPIO_76";
function = "rgmii_mdc";
bias-pull-up;
};
mdio {
pins = "GPIO_75";
function = "rgmii_mdio";
bias-pull-up;
};
tx {
pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64";
function = "rgmii_tx";
bias-pull-up;
drive-strength = <16>;
};
rx {
pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70";
function = "rgmii_rx";
bias-disable;
drive-strength = <2>;
};
tx-ctl {
pins = "GPIO_68";
function = "rgmii_ctl";
bias-pull-up;
drive-strength = <16>;
};
rx-ctl {
pins = "GPIO_74";
function = "rgmii_ctl";
bias-disable;
drive-strength = <2>;
};
tx-ck {
pins = "GPIO_63";
function = "rgmii_ck";
bias-pull-up;
drive-strength = <16>;
};
rx-ck {
pins = "GPIO_69";
function = "rgmii_ck";
bias-disable;
drive-strength = <2>;
};
};
};
blsp1_i2c0: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c0_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c1_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c2: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c2_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c3: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c3_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c4: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c4_default>;
#address-cells = <1>;
#size-cells = <0>;
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-qcs404";
reg = <0x1800000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <1>;
#reset-cells = <1>;
};
debug_uart: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b1000 0x200>;
clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
bit-rate = <0xFF>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp1_uart2>;
};
sdhci@7804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x7804000 0x1000 0x7805000 0x1000>;
clock = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
bus-width = <0x8>;
index = <0x0>;
non-removable;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
usb3_phy: phy@78000 {
compatible = "qcom,usb-ss-28nm-phy";
#phy-cells = <0>;
reg = <0x78000 0x400>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "ahb", "pipe";
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "com", "phy";
};
usb2_phy_prim: phy@7a000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7a000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
<&gcc GCC_USB2A_PHY_BCR>;
reset-names = "phy", "por";
};
usb2_phy_sec: phy@7c000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7c000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&gcc GCC_QUSB2_PHY_BCR>,
<&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
reset-names = "phy", "por";
};
usb3: usb@7678800 {
compatible = "qcom,dwc3";
reg = <0x7678800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@7580000 {
compatible = "snps,dwc3";
reg = <0x7580000 0xcd00>;
phys = <&usb2_phy_prim>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
};
usb2: usb@79b8800 {
compatible = "qcom,dwc3";
reg = <0x79b8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
<&gcc GCC_PCNOC_USB2_CLK>,
<&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@78c0000 {
compatible = "snps,dwc3";
reg = <0x78c0000 0xcc00>;
phys = <&usb2_phy_sec>;
phy-names = "usb2-phy";
dr_mode = "peripheral";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "high-speed";
};
};
ethernet: ethernet@7a80000 {
compatible = "qcom,qcs404-ethqos";
reg = <0x07a80000 0x10000>,
<0x07a96000 0x100>;
reg-names = "stmmaceth", "rgmii";
clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
clocks = <&gcc GCC_ETH_AXI_CLK>,
<&gcc GCC_ETH_SLAVE_AHB_CLK>,
<&gcc GCC_ETH_PTP_CLK>,
<&gcc GCC_ETH_RGMII_CLK>;
resets = <&gcc GCC_EMAC_BCR>;
reset-names = "emac";
snps,tso;
rx-fifo-depth = <4096>;
tx-fifo-depth = <4096>;
snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet_defaults>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
max-speed = <1000>;
mdio {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dwmac-mdio";
phy1: phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
reg = <0x3>;
};
};
};
spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x001000>,
<0x2400000 0x800000>,
<0x2c00000 0x800000>;
reg-names = "core", "chnls", "obsrvr";
#address-cells = <0x1>;
#size-cells = <0x1>;
pms405_0: pms405@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pms405_gpios: pms405_gpios@c000 {
compatible = "qcom,pms405-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-ranges = <&pms405_gpios 0 0 12>;
#gpio-cells = <2>;
};
};
};
};
};
#include "qcs404-evb-uboot.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, Linaro Limited
*/
#include <dt-bindings/gpio/gpio.h>
#include "qcs404.dtsi"
#include "pms405.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
aliases {
serial0 = &blsp1_uart2;
serial1 = &blsp1_uart3;
};
chosen {
stdout-path = "serial0";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
};
vdd_ch0_3p3:
vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
compatible = "regulator-fixed";
regulator-name = "eSMPS3_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
usb3_vbus_reg: regulator-usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "VBUS_BOOST_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_vbus_boost_pin>;
vin-supply = <&vph_pwr>;
enable-active-high;
/* TODO: Drop this when introducing role switching */
regulator-always-on;
};
};
&blsp1_uart3 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3990-bt";
vddio-supply = <&vreg_l6_1p8>;
vddxo-supply = <&vreg_l5_1p8>;
vddrf-supply = <&vreg_l1_1p3>;
vddch0-supply = <&vdd_ch0_3p3>;
local-bd-address = [ 02 00 00 00 5a ad ];
max-speed = <3200000>;
};
};
&blsp1_dma {
qcom,controlled-remotely;
};
&blsp2_dma {
qcom,controlled-remotely;
};
&gcc {
protected-clocks = <GCC_BIMC_CDSP_CLK>,
<GCC_CDSP_CFG_AHB_CLK>,
<GCC_CDSP_BIMC_CLK_SRC>,
<GCC_CDSP_TBU_CLK>,
<141>, /* GCC_WCSS_Q6_AHB_CLK */
<142>; /* GCC_WCSS_Q6_AXIM_CLK */
};
&pms405_spmi_regulators {
vdd_s3-supply = <&vph_pwr>;
pms405_s3: s3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_apc";
regulator-initial-mode = <1>;
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1384000>;
};
};
&pcie {
status = "okay";
perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&perst_state>;
};
&pcie_phy {
status = "okay";
vdda-vp-supply = <&vreg_l3_1p05>;
vdda-vph-supply = <&vreg_l5_1p8>;
};
&remoteproc_adsp {
status = "okay";
};
&remoteproc_cdsp {
status = "okay";
};
&remoteproc_wcss {
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pms405-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_l1_l2-supply = <&vreg_s5_1p35>;
vdd_l3_l8-supply = <&vreg_s5_1p35>;
vdd_l4-supply = <&vreg_s5_1p35>;
vdd_l5_l6-supply = <&vreg_s4_1p8>;
vdd_l7-supply = <&vph_pwr>;
vdd_l9-supply = <&vreg_s5_1p35>;
vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
vreg_s4_1p8: s4 {
regulator-min-microvolt = <1728000>;
regulator-max-microvolt = <1920000>;
};
vreg_s5_1p35: s5 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_l1_1p3: l1 {
regulator-min-microvolt = <1240000>;
regulator-max-microvolt = <1352000>;
};
vreg_l2_1p275: l2 {
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1280000>;
};
vreg_l3_1p05: l3 {
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1160000>;
};
vreg_l4_1p2: l4 {
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1256000>;
};
vreg_l5_1p8: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l6_1p8: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vreg_l7_1p8: l7 {
regulator-min-microvolt = <1616000>;
regulator-max-microvolt = <3000000>;
};
vreg_l8_1p2: l8 {
regulator-min-microvolt = <1136000>;
regulator-max-microvolt = <1352000>;
};
vreg_l10_3p3: l10 {
regulator-min-microvolt = <2936000>;
regulator-max-microvolt = <3088000>;
};
vreg_l11_sdc2: l11 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <3304000>;
};
vreg_l12_3p3: l12 {
regulator-min-microvolt = <3050000>;
regulator-max-microvolt = <3300000>;
};
vreg_l13_3p3: l13 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
};
};
&sdcc1 {
status = "okay";
supports-cqe;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&tlmm {
perst_state: perst-state {
pins = "gpio43";
function = "gpio";
drive-strength = <2>;
bias-disable;
output-low;
};
sdc1_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_off: sdc1-off-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
usb3_id_pin: usb3-id-state {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
&pms405_gpios {
usb_vbus_boost_pin: usb-vbus-boost-state {
pinconf {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
power-source = <1>;
};
};
usb3_vbus_pin: usb3-vbus-state {
pinconf {
pins = "gpio12";
function = PMIC_GPIO_FUNC_NORMAL;
input-enable;
bias-pull-down;
power-source = <1>;
};
};
};
&usb2 {
status = "okay";
};
&usb2_phy_sec {
vdd-supply = <&vreg_l4_1p2>;
vdda1p8-supply = <&vreg_l5_1p8>;
vdda3p3-supply = <&vreg_l12_3p3>;
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "host";
};
&usb2_phy_prim {
vdd-supply = <&vreg_l4_1p2>;
vdda1p8-supply = <&vreg_l5_1p8>;
vdda3p3-supply = <&vreg_l12_3p3>;
status = "okay";
};
&usb3_phy {
vdd-supply = <&vreg_l3_1p05>;
vdda1p8-supply = <&vreg_l5_1p8>;
status = "okay";
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
vdd-1.8-xo-supply = <&vreg_l5_1p8>;
vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
};
/* PINCTRL - additions to nodes defined in qcs404.dtsi */
&blsp1_uart2_default {
rx-pins {
drive-strength = <2>;
bias-disable;
};
tx-pins {
drive-strength = <2>;
bias-disable;
};
};
&blsp1_uart3_default {
cts-pins {
bias-disable;
};
rts-tx-pins {
drive-strength = <2>;
bias-disable;
};
rx-pins {
bias-pull-up;
};
};

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// SPDX-License-Identifier: GPL-2.0
/ {
chosen {
stdout-path = "serial0:921600n8";
};
};
&tlmm {
muic-i2c-n {
pins = "gpio33", "gpio34";
drive-strength = <0x2>;
function = "gpio";
bias-disable;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sdm845.dtsi"
/ {
chassis-type = "handset";
model = "Samsung Galaxy S9 SM-G9600";
compatible = "samsung,starqltechn", "qcom,sdm845";
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer: framebuffer@9d400000 {
compatible = "simple-framebuffer";
reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000
width = <1440>;
height = <2960>;
stride = <(1440 * 4)>;
format = "a8r8g8b8";
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
/*
* Apparently RPMh does not provide support for PM8998 S4 because it
* is always-on; model it as a fixed regulator.
*/
vreg_s4a_1p8: pm8998-smps4 {
compatible = "regulator-fixed";
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vph_pwr>;
};
reserved-memory {
memory@9d400000 {
reg = <0x0 0x9d400000 0x0 0x02400000>;
no-map;
};
memory@a1300000 {
compatible = "ramoops";
reg = <0x0 0xa1300000 0x0 0x100000>;
record-size = <0x40000>;
console-size = <0x40000>;
ftrace-size = <0x40000>;
pmsg-size = <0x40000>;
};
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-s11-supply = <&vph_pwr>;
vdd-s12-supply = <&vph_pwr>;
vdd-s13-supply = <&vph_pwr>;
vdd-l1-l27-supply = <&vreg_s7a_1p025>;
vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
vdd-l3-l11-supply = <&vreg_s7a_1p025>;
vdd-l4-l5-supply = <&vreg_s7a_1p025>;
vdd-l6-supply = <&vph_pwr>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
vdd-l26-supply = <&vreg_s3a_1p35>;
vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
vreg_s2a_1p125: smps2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
vreg_s3a_1p35: smps3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_s5a_2p04: smps5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2040000>;
};
vreg_s7a_1p025: smps7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
vdd_qusb_hs0:
vdda_hp_pcie_core:
vdda_mipi_csi0_0p9:
vdda_mipi_csi1_0p9:
vdda_mipi_csi2_0p9:
vdda_mipi_dsi0_pll:
vdda_mipi_dsi1_pll:
vdda_qlink_lv:
vdda_qlink_lv_ck:
vdda_qrefs_0p875:
vdda_pcie_core:
vdda_pll_cc_ebi01:
vdda_pll_cc_ebi23:
vdda_sp_sensor:
vdda_ufs1_core:
vdda_ufs2_core:
vdda_usb1_ss_core:
vdda_usb2_ss_core:
vreg_l1a_0p875: ldo1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_10:
vreg_l2a_1p2: ldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l3a_1p0: ldo3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_wcss_cx:
vdd_wcss_mx:
vdda_wcss_pll:
vreg_l5a_0p8: ldo5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_13:
vreg_l6a_1p8: ldo6 {
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <1856000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a_1p2: ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1248000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a_1p8: ldo9 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10a_1p8: ldo10 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a_1p0: ldo11 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1048000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_qfprom:
vdd_qfprom_sp:
vdda_apc1_cs_1p8:
vdda_gfx_cs_1p8:
vdda_qrefs_1p8:
vdda_qusb_hs0_1p8:
vddpx_11:
vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_2:
vreg_l13a_2p95: ldo13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14a_1p88: ldo14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a_1p8: ldo15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16a_2p7: ldo16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17a_1p3: ldo17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_2p7: ldo18 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19a_3p0: ldo19 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20a_2p95: ldo20 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l21a_2p95: ldo21 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l22a_2p85: ldo22 {
regulator-min-microvolt = <2864000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l23a_3p3: ldo23 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
vreg_l24a_3p075: ldo24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l25a_3p3: ldo25 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_hp_pcie_1p2:
vdda_hv_ebi0:
vdda_hv_ebi1:
vdda_hv_ebi2:
vdda_hv_ebi3:
vdda_mipi_csi_1p25:
vdda_mipi_dsi0_1p2:
vdda_mipi_dsi1_1p2:
vdda_pcie_1p2:
vdda_ufs1_1p2:
vdda_ufs2_1p2:
vdda_usb1_ss_1p2:
vdda_usb2_ss_1p2:
vreg_l26a_1p2: ldo26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l28a_3p0: ldo28 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs2a_1p8: lvs2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
regulators-1 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vreg_s3c_0p6: smps3 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
};
};
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
&i2c10 {
clock-frequency = <400000>;
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&uart9 {
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l20a_2p95>;
vcc-max-microamp = <600000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vdda_ufs1_core>;
vdda-pll-supply = <&vdda_ufs1_1p2>;
status = "okay";
};
&sdhc_2 {
pinctrl-names = "default";
pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>;
cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vddpx_2>;
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
/* Until we have Type C hooked up we'll force this as peripheral. */
dr_mode = "peripheral";
};
&usb_1_hsphy {
vdd-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
qcom,imp-res-offset-value = <8>;
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
status = "okay";
};
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>;
sdc2_clk_state: sdc2-clk-state {
pins = "sdc2_clk";
bias-disable;
/*
* It seems that mmc_test reports errors if drive
* strength is not 16 on clk, cmd, and data pins.
*/
drive-strength = <16>;
};
sdc2_cmd_state: sdc2-cmd-state {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <16>;
};
sdc2_data_state: sdc2-data-state {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <16>;
};
sd_card_det_n_state: sd-card-det-n-state {
pins = "gpio126";
function = "gpio";
bias-pull-up;
};
};

86
arch/arm/dts/sdm845-wcd9340.dtsi Normal file
View file

@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SDM845 SoC device tree source
*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
&slim {
status = "okay";
slim@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
wcd9340_ifd: ifd@0,0 {
compatible = "slim217,250";
reg = <0 0>;
};
wcd9340: codec@1,0 {
compatible = "slim217,250";
reg = <1 0>;
slim-ifc-dev = <&wcd9340_ifd>;
#sound-dai-cells = <1>;
interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
#clock-cells = <0>;
clock-frequency = <9600000>;
clock-output-names = "mclk";
pinctrl-0 = <&wcd_intr_default>;
pinctrl-names = "default";
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
#address-cells = <1>;
#size-cells = <1>;
wcdgpio: gpio-controller@42 {
compatible = "qcom,wcd9340-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42 0x2>;
};
swm: swm@c85 {
compatible = "qcom,soundwire-v1.3.0";
reg = <0xc85 0x40>;
interrupts-extended = <&wcd9340 20>;
qcom,dout-ports = <6>;
qcom,din-ports = <2>;
qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>;
#sound-dai-cells = <1>;
clocks = <&wcd9340>;
clock-names = "iface";
#address-cells = <2>;
#size-cells = <0>;
};
};
};
};
&tlmm {
wcd_intr_default: wcd-intr-default-state {
pins = "gpio54";
function = "gpio";
bias-pull-down;
drive-strength = <2>;
};
};

5801
arch/arm/dts/sdm845.dtsi
View file

File diff suppressed because it is too large Load diff

27
arch/arm/dts/starqltechn-uboot.dtsi
View file

@ -1,27 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins
*
* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
*
*/
/
{
framebuffer@9D400000 {
bootph-all;
};
soc {
bootph-all;
serial@a84000 {
bootph-all;
};
clock-controller@100000 {
bootph-all;
};
pinctrl@3400000 {
bootph-all;
};
};
};

68
arch/arm/dts/starqltechn.dts
View file

@ -1,68 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Samsung S9 SM-G9600 (starqltechn) board device tree source
*
* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
*
*/
/dts-v1/;
#include "sdm845.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Samsung S9 (SM-G9600)";
compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "serial0:921600n8";
};
aliases {
serial0 = &uart9;
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xfe1bffff>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
framebuffer: framebuffer@9D400000 {
compatible = "simple-framebuffer";
reg = <0 0x9D400000 0 (2960 * 1440 * 4)>;//2400000
width = <1440>;
height = <2960>;
stride = <(1440 * 4)>;
format = "a8r8g8b8";
};
soc: soc {
serial@a84000 {
status = "okay";
};
};
};
&pm8998_resin {
status = "okay";
};
&tlmm {
muic_i2c: muic-i2c-n {
pins = "GPIO_33", "GPIO_34";
drive-strength = <0x2>;
function = "gpio";
bias-disable;
};
};
#include "starqltechn-uboot.dtsi"

5
arch/arm/lib/save_prev_bl_data.c
View file

@ -45,6 +45,11 @@ bool is_addr_accessible(phys_addr_t addr)
return false;
}
phys_addr_t get_prev_bl_fdt_addr(void)
{
return reg0;
}
int save_prev_bl_data(void)
{
struct fdt_header *fdt_blob;

95
arch/arm/mach-snapdragon/Kconfig
View file

@ -3,6 +3,9 @@ if ARCH_SNAPDRAGON
config SYS_SOC
default "snapdragon"
config SYS_VENDOR
default "qualcomm"
config SYS_MALLOC_F_LEN
default 0x2000
@ -12,90 +15,24 @@ config SPL_SYS_MALLOC_F
config SPL_SYS_MALLOC_F_LEN
default 0x2000
config SDM845
bool "Qualcomm Snapdragon 845 SoC"
select LINUX_KERNEL_IMAGE_HEADER
imply CLK_QCOM_SDM845
imply PINCTRL_QCOM_SDM845
imply BUTTON_QCOM_PMIC
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default 0x80000000
choice
prompt "Snapdragon board select"
config TARGET_DRAGONBOARD410C
bool "96Boards Dragonboard 410C"
select BOARD_LATE_INIT
select ENABLE_ARM_SOC_BOOT0_HOOK
imply CLK_QCOM_APQ8016
imply PINCTRL_QCOM_APQ8016
imply BUTTON_QCOM_PMIC
config SYS_BOARD
string "Qualcomm custom board"
help
Support for 96Boards Dragonboard 410C. This board complies with
96Board Open Platform Specifications. Features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 1GiB RAM
- 8GiB eMMC, uSD slot
- WiFi, Bluetooth and GPS module
- 2x Host, 1x Device USB port
- HDMI
- 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
The Dragonboard 410c and 820c have additional board init
code that isn't shared with other Qualcomm boards.
Based on this option board/qualcomm/<CONFIG_SYS_BOARD> will
be used.
config TARGET_DRAGONBOARD820C
bool "96Boards Dragonboard 820C"
imply CLK_QCOM_APQ8096
imply PINCTRL_QCOM_APQ8096
imply BUTTON_QCOM_PMIC
config SYS_CONFIG_NAME
string "Board configuration name"
default SYS_BOARD if SYS_BOARD != ""
default "qcom"
help
Support for 96Boards Dragonboard 820C. This board complies with
96Board Open Platform Specifications. Features:
- Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU)
- 3GiB RAM
- 32GiB UFS drive
config TARGET_DRAGONBOARD845C
bool "96Boards Dragonboard 845C"
help
Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
Platform. This board complies with 96Boards Open Platform
Specifications. Features:
- Qualcomm Snapdragon SDA845 SoC
- 4GiB RAM
- 64GiB UFS drive
select MISC_INIT_R
select SDM845
config TARGET_STARQLTECHN
bool "Samsung S9 SM-G9600(starqltechn)"
help
Support for Samsung S9 SM-G9600(starqltechn) board.
Features:
- Qualcomm Snapdragon SDM845 SoC
- 4GiB RAM
- 64GiB UFS drive
select MISC_INIT_R
select SDM845
config TARGET_QCS404EVB
bool "Qualcomm Technologies, Inc. QCS404 EVB"
select LINUX_KERNEL_IMAGE_HEADER
imply CLK_QCOM_QCS404
imply PINCTRL_QCOM_QCS404
help
Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot
endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
source "board/qualcomm/dragonboard820c/Kconfig"
source "board/qualcomm/dragonboard845c/Kconfig"
source "board/samsung/starqltechn/Kconfig"
source "board/qualcomm/qcs404-evb/Kconfig"
This option contains information about board configuration name.
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
endif

8
arch/arm/mach-snapdragon/Makefile
View file

@ -2,10 +2,4 @@
#
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
obj-$(CONFIG_SDM845) += sysmap-sdm845.o
obj-$(CONFIG_SDM845) += init_sdm845.o
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
obj-y += misc.o
obj-y += dram.o
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
obj-y += board.o

468
arch/arm/mach-snapdragon/board.c Normal file
View file

@ -0,0 +1,468 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Common initialisation for Qualcomm Snapdragon boards.
*
* Copyright (c) 2024 Linaro Ltd.
* Author: Caleb Connolly <caleb.connolly@linaro.org>
*/
#include "time.h"
#include <asm/armv8/mmu.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/system.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
#include <dm/read.h>
#include <env.h>
#include <init.h>
#include <linux/arm-smccc.h>
#include <linux/bug.h>
#include <linux/psci.h>
#include <linux/sizes.h>
#include <lmb.h>
#include <malloc.h>
#include <usb.h>
#include <sort.h>
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
struct mm_region *mem_map = rbx_mem_map;
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
static int ddr_bank_cmp(const void *v1, const void *v2)
{
const struct {
phys_addr_t start;
phys_size_t size;
} *res1 = v1, *res2 = v2;
if (!res1->size)
return 1;
if (!res2->size)
return -1;
return (res1->start >> 24) - (res2->start >> 24);
}
int dram_init_banksize(void)
{
int ret;
ret = fdtdec_setup_memory_banksize();
if (ret < 0)
return ret;
if (CONFIG_NR_DRAM_BANKS < 2)
return 0;
/* Sort our RAM banks -_- */
qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp);
return 0;
}
static void show_psci_version(void)
{
struct arm_smccc_res res;
arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
debug("PSCI: v%ld.%ld\n",
PSCI_VERSION_MAJOR(res.a0),
PSCI_VERSION_MINOR(res.a0));
}
void *board_fdt_blob_setup(int *err)
{
phys_addr_t fdt;
/* Return DTB pointer passed by ABL */
*err = 0;
fdt = get_prev_bl_fdt_addr();
/*
* If we bail then the board will simply not boot, instead let's
* try and use the FDT built into U-Boot if there is one...
* This avoids having a hard dependency on the previous stage bootloader
*/
if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
return (void *)gd->fdt_blob;
}
return (void *)fdt;
}
void reset_cpu(void)
{
psci_system_reset();
}
/*
* Some Qualcomm boards require GPIO configuration when switching USB modes.
* Support setting this configuration via pinctrl state.
*/
int board_usb_init(int index, enum usb_init_type init)
{
struct udevice *usb;
int ret = 0;
/* USB device */
ret = uclass_find_device_by_seq(UCLASS_USB, index, &usb);
if (ret) {
printf("Cannot find USB device\n");
return ret;
}
ret = dev_read_stringlist_search(usb, "pinctrl-names",
"device");
/* No "device" pinctrl state, so just bail */
if (ret < 0)
return 0;
/* Select "default" or "device" pinctrl */
switch (init) {
case USB_INIT_HOST:
pinctrl_select_state(usb, "default");
break;
case USB_INIT_DEVICE:
pinctrl_select_state(usb, "device");
break;
default:
debug("Unknown usb_init_type %d\n", init);
break;
}
return 0;
}
/*
* Some boards still need board specific init code, they can implement that by
* overriding this function.
*
* FIXME: get rid of board specific init code
*/
void __weak qcom_board_init(void)
{
}
int board_init(void)
{
show_psci_version();
qcom_board_init();
return 0;
}
/* Sets up the "board", and "soc" environment variables as well as constructing the devicetree
* path, with a few quirks to handle non-standard dtb filenames. This is not meant to be a
* comprehensive solution to automatically picking the DTB, but aims to be correct for the
* majority case. For most devices it should be possible to make this algorithm work by
* adjusting the root compatible property in the U-Boot DTS. Handling devices with multiple
* variants that are all supported by a single U-Boot image will require implementing device-
* specific detection.
*/
static void configure_env(void)
{
const char *first_compat, *last_compat;
char *tmp;
char buf[32] = { 0 };
/*
* Most DTB filenames follow the scheme: qcom/<soc>-[vendor]-<board>.dtb
* The vendor is skipped when it's a Qualcomm reference board, or the
* db845c.
*/
char dt_path[64] = { 0 };
int compat_count, ret;
ofnode root;
root = ofnode_root();
/* This is almost always 2, but be explicit that we want the first and last compatibles
* not the first and second.
*/
compat_count = ofnode_read_string_count(root, "compatible");
if (compat_count < 2) {
log_warning("%s: only one root compatible bailing!\n", __func__);
return;
}
/* The most specific device compatible (e.g. "thundercomm,db845c") */
ret = ofnode_read_string_index(root, "compatible", 0, &first_compat);
if (ret < 0) {
log_warning("Can't read first compatible\n");
return;
}
/* The last compatible is always the SoC compatible */
ret = ofnode_read_string_index(root, "compatible", compat_count - 1, &last_compat);
if (ret < 0) {
log_warning("Can't read second compatible\n");
return;
}
/* Copy the second compat (e.g. "qcom,sdm845") into buf */
strlcpy(buf, last_compat, sizeof(buf) - 1);
tmp = buf;
/* strsep() is destructive, it replaces the comma with a \0 */
if (!strsep(&tmp, ",")) {
log_warning("second compatible '%s' has no ','\n", buf);
return;
}
/* tmp now points to just the "sdm845" part of the string */
env_set("soc", tmp);
/* Now figure out the "board" part from the first compatible */
memset(buf, 0, sizeof(buf));
strlcpy(buf, first_compat, sizeof(buf) - 1);
tmp = buf;
/* The Qualcomm reference boards (RBx, HDK, etc) */
if (!strncmp("qcom", buf, strlen("qcom"))) {
/*
* They all have the first compatible as "qcom,<soc>-<board>"
* (e.g. "qcom,qrb5165-rb5"). We extract just the part after
* the dash.
*/
if (!strsep(&tmp, "-")) {
log_warning("compatible '%s' has no '-'\n", buf);
return;
}
/* tmp is now "rb5" */
env_set("board", tmp);
} else {
if (!strsep(&tmp, ",")) {
log_warning("compatible '%s' has no ','\n", buf);
return;
}
/* for thundercomm we just want the bit after the comma (e.g. "db845c"),
* for all other boards we replace the comma with a '-' and take both
* (e.g. "oneplus-enchilada")
*/
if (!strncmp("thundercomm", buf, strlen("thundercomm"))) {
env_set("board", tmp);
} else {
*(tmp - 1) = '-';
env_set("board", buf);
}
}
/* Now build the full path name */
snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb",
env_get("soc"), env_get("board"));
env_set("fdtfile", dt_path);
}
void __weak qcom_late_init(void)
{
}
#define KERNEL_COMP_SIZE SZ_64M
#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
/* Stolen from arch/arm/mach-apple/board.c */
int board_late_init(void)
{
struct lmb lmb;
u32 status = 0;
lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
/* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */
status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M));
status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M));
status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb, KERNEL_COMP_SIZE));
status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M));
status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M));
status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M));
if (status)
log_warning("%s: Failed to set run time variables\n", __func__);
configure_env();
qcom_late_init();
return 0;
}
static void build_mem_map(void)
{
int i, j;
/*
* Ensure the peripheral block is sized to correctly cover the address range
* up to the first memory bank.
* Don't map the first page to ensure that we actually trigger an abort on a
* null pointer access rather than just hanging.
* FIXME: we should probably split this into more precise regions
*/
mem_map[0].phys = 0x1000;
mem_map[0].virt = mem_map[0].phys;
mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN;
for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) {
mem_map[i].phys = gd->bd->bi_dram[j].start;
mem_map[i].virt = mem_map[i].phys;
mem_map[i].size = gd->bd->bi_dram[j].size;
mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
PTE_BLOCK_INNER_SHARE;
}
mem_map[i].phys = UINT64_MAX;
mem_map[i].size = 0;
#ifdef DEBUG
debug("Configured memory map:\n");
for (i = 0; mem_map[i].size; i++)
debug(" 0x%016llx - 0x%016llx: entry %d\n",
mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i);
#endif
}
u64 get_page_table_size(void)
{
return SZ_64K;
}
static int fdt_cmp_res(const void *v1, const void *v2)
{
const struct fdt_resource *res1 = v1, *res2 = v2;
return res1->start - res2->start;
}
#define N_RESERVED_REGIONS 32
/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access.
* On some platforms this is enough to trigger a security violation and trap
* to EL3.
*/
static void carve_out_reserved_memory(void)
{
static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 };
int parent, rmem, count, i = 0;
phys_addr_t start;
size_t size;
/* Some reserved nodes must be carved out, as the cache-prefetcher may otherwise
* attempt to access them, causing a security exception.
*/
parent = fdt_path_offset(gd->fdt_blob, "/reserved-memory");
if (parent <= 0) {
log_err("No reserved memory regions found\n");
return;
}
/* Collect the reserved memory regions */
fdt_for_each_subnode(rmem, gd->fdt_blob, parent) {
const fdt32_t *ptr;
int len;
if (!fdt_getprop(gd->fdt_blob, rmem, "no-map", NULL))
continue;
if (i == N_RESERVED_REGIONS) {
log_err("Too many reserved regions!\n");
break;
}
/* Read the address and size out from the reg property. Doing this "properly" with
* fdt_get_resource() takes ~70ms on SDM845, but open-coding the happy path here
* takes <1ms... Oh the woes of no dcache.
*/
ptr = fdt_getprop(gd->fdt_blob, rmem, "reg", &len);
if (ptr) {
/* Qualcomm devices use #address/size-cells = <2> but all reserved regions are within
* the 32-bit address space. So we can cheat here for speed.
*/
res[i].start = fdt32_to_cpu(ptr[1]);
res[i].end = res[i].start + fdt32_to_cpu(ptr[3]);
i++;
}
}
/* Sort the reserved memory regions by address */
count = i;
qsort(res, count, sizeof(struct fdt_resource), fdt_cmp_res);
/* Now set the right attributes for them. Often a lot of the regions are tightly packed together
* so we can optimise the number of calls to mmu_change_region_attr() by combining adjacent
* regions.
*/
start = ALIGN_DOWN(res[0].start, SZ_2M);
size = ALIGN(res[0].end - start, SZ_2M);
for (i = 1; i <= count; i++) {
/* We ideally want to 2M align everything for more efficient pagetables, but we must avoid
* overwriting reserved memory regions which shouldn't be mapped as FAULT (like those with
* compatible properties).
* If within 2M of the previous region, bump the size to include this region. Otherwise
* start a new region.
*/
if (i == count || start + size < res[i].start - SZ_2M) {
debug(" 0x%016llx - 0x%016llx: reserved\n",
start, start + size);
mmu_change_region_attr(start, size, PTE_TYPE_FAULT);
/* If this is the final region then quit here before we index
* out of bounds...
*/
if (i == count)
break;
start = ALIGN_DOWN(res[i].start, SZ_2M);
size = ALIGN(res[i].end - start, SZ_2M);
} else {
/* Bump size if this region is immediately after the previous one */
size = ALIGN(res[i].end - start, SZ_2M);
}
}
}
/* This function open-codes setup_all_pgtables() so that we can
* insert additional mappings *before* turning on the MMU.
*/
void enable_caches(void)
{
u64 tlb_addr = gd->arch.tlb_addr;
u64 tlb_size = gd->arch.tlb_size;
u64 pt_size;
ulong carveout_start;
gd->arch.tlb_fillptr = tlb_addr;
build_mem_map();
icache_enable();
/* Create normal system page tables */
setup_pgtables();
pt_size = (uintptr_t)gd->arch.tlb_fillptr -
(uintptr_t)gd->arch.tlb_addr;
debug("Primary pagetable size: %lluKiB\n", pt_size / 1024);
/* Create emergency page tables */
gd->arch.tlb_size -= pt_size;
gd->arch.tlb_addr = gd->arch.tlb_fillptr;
setup_pgtables();
gd->arch.tlb_emerg = gd->arch.tlb_addr;
gd->arch.tlb_addr = tlb_addr;
gd->arch.tlb_size = tlb_size;
carveout_start = get_timer(0);
/* Takes ~20-50ms on SDM845 */
carve_out_reserved_memory();
debug("carveout time: %lums\n", get_timer(carveout_start));
dcache_enable();
}

99
arch/arm/mach-snapdragon/dram.c
View file

@ -1,99 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Onboard memory detection for Snapdragon boards
*
* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
*
*/
#include <common.h>
#include <dm.h>
#include <log.h>
#include <part.h>
#include <smem.h>
#include <fdt_support.h>
#include <asm/arch/dram.h>
#define SMEM_USABLE_RAM_PARTITION_TABLE 402
#define RAM_PART_NAME_LENGTH 16
#define RAM_NUM_PART_ENTRIES 32
#define CATEGORY_SDRAM 0x0E
#define TYPE_SYSMEM 0x01
struct smem_ram_ptable_hdr {
u32 magic[2];
u32 version;
u32 reserved;
u32 len;
} __attribute__ ((__packed__));
struct smem_ram_ptn {
char name[RAM_PART_NAME_LENGTH];
u64 start;
u64 size;
u32 attr;
u32 category;
u32 domain;
u32 type;
u32 num_partitions;
u32 reserved[3];
} __attribute__ ((__packed__));
struct smem_ram_ptable {
struct smem_ram_ptable_hdr hdr;
u32 reserved; /* Added for 8 bytes alignment of header */
struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES];
} __attribute__ ((__packed__));
#ifndef MEMORY_BANKS_MAX
#define MEMORY_BANKS_MAX 4
#endif
int msm_fixup_memory(void *blob)
{
u64 bank_start[MEMORY_BANKS_MAX];
u64 bank_size[MEMORY_BANKS_MAX];
size_t size;
int i;
int count = 0;
struct udevice *smem;
int ret;
struct smem_ram_ptable *ram_ptable;
struct smem_ram_ptn *p;
ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", &smem);
if (ret < 0) {
printf("Failed to find SMEM node. Check device tree\n");
return 0;
}
ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, &size);
if (!ram_ptable) {
printf("Failed to find SMEM partition.\n");
return -ENODEV;
}
/* Check validy of RAM */
for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) {
p = &ram_ptable->parts[i];
if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) {
bank_start[count] = p->start;
bank_size[count] = p->size;
debug("Detected memory bank %u: start: 0x%llx size: 0x%llx\n",
count, p->start, p->size);
count++;
}
}
if (!count) {
printf("Failed to detect any memory bank\n");
return -ENODEV;
}
ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count);
if (ret)
return ret;
return 0;
}

12
arch/arm/mach-snapdragon/include/mach/dram.h
View file

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Snapdragon DRAM
* Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
*/
#ifndef DRAM_H
#define DRAM_H
int msm_fixup_memory(void *blob);
#endif

7
arch/arm/mach-snapdragon/include/mach/gpio.h
View file

@ -13,6 +13,8 @@
struct msm_pin_data {
int pin_count;
const unsigned int *pin_offsets;
/* Index of first special pin, these are ignored for now */
unsigned int special_pins_start;
};
static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
@ -25,4 +27,9 @@ static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selecto
return out;
}
static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin)
{
return pindata->special_pins_start && pin >= pindata->special_pins_start;
}
#endif /* _QCOM_GPIO_H_ */

13
arch/arm/mach-snapdragon/include/mach/misc.h
View file

@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Snapdragon DRAM
* Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
*/
#ifndef MISC_H
#define MISC_H
u32 msm_board_serial(void);
void msm_generate_mac_addr(u8 *mac);
#endif

73
arch/arm/mach-snapdragon/init_sdm845.c
View file

@ -1,73 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Common init part for boards based on SDM845
*
* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
*/
#include <button.h>
#include <init.h>
#include <env.h>
#include <common.h>
#include <asm/system.h>
#include <asm/gpio.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
void reset_cpu(void)
{
psci_system_reset();
}
__weak int board_init(void)
{
return 0;
}
/* Check for vol- and power buttons */
__weak int misc_init_r(void)
{
struct udevice *btn;
int ret;
enum button_state_t state;
ret = button_get_by_label("pwrkey", &btn);
if (ret < 0) {
printf("Couldn't find power button!\n");
return ret;
}
state = button_get_state(btn);
if (state == BUTTON_ON) {
env_set("key_power", "1");
printf("Power button pressed\n");
} else {
env_set("key_power", "0");
}
/*
* search for kaslr address, set by primary bootloader by searching first
* 0x100 relocated bytes at u-boot's initial load address range
*/
uintptr_t start = gd->ram_base;
uintptr_t end = start + 0x800000;
u8 *addr = (u8 *)start;
phys_addr_t *relocaddr = (phys_addr_t *)gd->relocaddr;
u32 block_size = 0x1000;
while (memcmp(addr, relocaddr, 0x100) && (uintptr_t)addr < end)
addr += block_size;
if ((uintptr_t)addr >= end)
printf("KASLR not found in range 0x%lx - 0x%lx", start, end);
else
env_set_addr("KASLR", addr);
return 0;
}

55
arch/arm/mach-snapdragon/misc.c
View file

@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Miscellaneous Snapdragon functionality
*
* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
*
*/
#include <common.h>
#include <mmc.h>
#include <asm/arch/misc.h>
#include <asm/unaligned.h>
/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
#define UNSTUFF_BITS(resp, start, size) \
({ \
const int __size = size; \
const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
const int __off = 3 - ((start) / 32); \
const int __shft = (start) & 31; \
u32 __res; \
\
__res = resp[__off] >> __shft; \
if (__size + __shft > 32) \
__res |= resp[__off - 1] << ((32 - __shft) % 32); \
__res & __mask; \
})
u32 msm_board_serial(void)
{
struct mmc *mmc_dev;
mmc_dev = find_mmc_device(0);
if (!mmc_dev)
return 0;
if (mmc_init(mmc_dev))
return 0;
return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
}
void msm_generate_mac_addr(u8 *mac)
{
/* use locally adminstrated pool */
mac[0] = 0x02;
mac[1] = 0x00;
/*
* Put the 32-bit serial number in the last 32-bit of the MAC address.
* Use big endian order so it is consistent with the serial number
* written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd
*/
put_unaligned_be32(msm_board_serial(), &mac[2]);
}

31
arch/arm/mach-snapdragon/sysmap-apq8016.c
View file

@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm APQ8016 memory map
*
* (C) Copyright 2016 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region apq8016_mem_map[] = {
{
.virt = 0x0UL, /* Peripheral block */
.phys = 0x0UL, /* Peripheral block */
.size = 0x8000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL, /* DDR */
.phys = 0x80000000UL, /* DDR */
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = apq8016_mem_map;

31
arch/arm/mach-snapdragon/sysmap-apq8096.c
View file

@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm APQ8096 memory map
*
* (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region apq8096_mem_map[] = {
{
.virt = 0x0UL, /* Peripheral block */
.phys = 0x0UL, /* Peripheral block */
.size = 0x10000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL, /* DDR */
.phys = 0x80000000UL, /* DDR */
.size = 0xC0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = apq8096_mem_map;

43
arch/arm/mach-snapdragon/sysmap-qcs404.c
View file

@ -1,43 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm QCS404 memory map
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region qcs404_mem_map[] = {
{
.virt = 0x0UL, /* Peripheral block */
.phys = 0x0UL, /* Peripheral block */
.size = 0x8000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL, /* DDR */
.phys = 0x80000000UL, /* DDR */
.size = 0x05900000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x89600000UL, /* DDR */
.phys = 0x89600000UL, /* DDR */
.size = 0x162000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL, /* DDR */
.phys = 0xa0000000UL, /* DDR */
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = qcs404_mem_map;

31
arch/arm/mach-snapdragon/sysmap-sdm845.c
View file

@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm SDM845 memory map
*
* (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com>
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region sdm845_mem_map[] = {
{
.virt = 0x0UL, /* Peripheral block */
.phys = 0x0UL, /* Peripheral block */
.size = 0x10000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL, /* DDR */
.phys = 0x80000000UL, /* DDR */
.size = 0x200000000UL, /* 8GiB - maximum allowed memory */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = sdm845_mem_map;

9
arch/sandbox/dts/sandbox.dtsi
View file

@ -419,17 +419,16 @@
#size-cells = <0x1>;
pm8916@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
reg = <0x0 0x0>;
#address-cells = <0x1>;
#size-cells = <0x1>;
#size-cells = <0x0>;
spmi_gpios: gpios@c000 {
compatible = "qcom,pm8916-gpio";
reg = <0xc000 0x400>;
reg = <0xc000>;
gpio-controller;
gpio-count = <4>;
gpio-ranges = <&spmi_gpios 0 0 4>;
#gpio-cells = <2>;
gpio-bank-name="spmi";
};
};
};

15
board/qualcomm/dragonboard410c/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_DRAGONBOARD410C
config SYS_BOARD
default "dragonboard410c"
config SYS_VENDOR
default "qualcomm"
config SYS_SOC
default "apq8016"
config SYS_CONFIG_NAME
default "dragonboard410c"
endif

2
board/qualcomm/dragonboard410c/Makefile
View file

@ -2,4 +2,4 @@
#
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
obj-y := dragonboard410c.o
obj-y := dragonboard410c.o

7
board/qualcomm/dragonboard410c/configs/chainloaded.config Normal file
View file

@ -0,0 +1,7 @@
# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
CONFIG_TEXT_BASE=0x0
# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set
# CONFIG_REMAKE_ELF is not set
CONFIG_POSITION_INDEPENDENT=y
CONFIG_INIT_SP_RELATIVE=y
CONFIG_SYS_INIT_SP_BSS_OFFSET=524288

130
board/qualcomm/dragonboard410c/dragonboard410c.c
View file

@ -9,101 +9,61 @@
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <env.h>
#include <init.h>
#include <mmc.h>
#include <net.h>
#include <usb.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <fdt_support.h>
#include <asm/arch/dram.h>
#include <asm/arch/misc.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
#define UNSTUFF_BITS(resp, start, size) \
({ \
const int __size = size; \
const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
const int __off = 3 - ((start) / 32); \
const int __shft = (start) & 31; \
u32 __res; \
\
__res = resp[__off] >> __shft; \
if (__size + __shft > 32) \
__res |= resp[__off - 1] << ((32 - __shft) % 32); \
__res & __mask; \
})
return 0;
static u32 msm_board_serial(void)
{
struct mmc *mmc_dev;
mmc_dev = find_mmc_device(0);
if (!mmc_dev)
return 0;
if (mmc_init(mmc_dev))
return 0;
return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
}
int dram_init_banksize(void)
static void msm_generate_mac_addr(u8 *mac)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
/* use locally adminstrated pool */
mac[0] = 0x02;
mac[1] = 0x00;
return 0;
}
int board_usb_init(int index, enum usb_init_type init)
{
static struct udevice *pmic_gpio;
static struct gpio_desc hub_reset, usb_sel;
int ret = 0, node;
if (!pmic_gpio) {
ret = uclass_get_device_by_name(UCLASS_GPIO,
"pm8916_gpios@c000",
&pmic_gpio);
if (ret < 0) {
printf("Failed to find pm8916_gpios@c000 node.\n");
return ret;
}
}
/* Try to request gpios needed to start usb host on dragonboard */
if (!dm_gpio_is_valid(&hub_reset)) {
node = fdt_subnode_offset(gd->fdt_blob,
dev_of_offset(pmic_gpio),
"usb_hub_reset_pm");
if (node < 0) {
printf("Failed to find usb_hub_reset_pm dt node.\n");
return node;
}
ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
"gpios", 0, &hub_reset, 0);
if (ret < 0) {
printf("Failed to request usb_hub_reset_pm gpio.\n");
return ret;
}
}
if (!dm_gpio_is_valid(&usb_sel)) {
node = fdt_subnode_offset(gd->fdt_blob,
dev_of_offset(pmic_gpio),
"usb_sw_sel_pm");
if (node < 0) {
printf("Failed to find usb_sw_sel_pm dt node.\n");
return 0;
}
ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
"gpios", 0, &usb_sel, 0);
if (ret < 0) {
printf("Failed to request usb_sw_sel_pm gpio.\n");
return ret;
}
}
if (init == USB_INIT_HOST) {
/* Start USB Hub */
dm_gpio_set_dir_flags(&hub_reset,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
mdelay(100);
/* Switch usb to host connectors */
dm_gpio_set_dir_flags(&usb_sel,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
mdelay(100);
} else { /* Device */
/* Disable hub */
dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT);
/* Switch back to device connector */
dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT);
}
return 0;
/*
* Put the 32-bit serial number in the last 32-bit of the MAC address.
* Use big endian order so it is consistent with the serial number
* written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd
*/
put_unaligned_be32(msm_board_serial(), &mac[2]);
}
/* Check for vol- button - if pressed - stop autoboot */
@ -128,12 +88,7 @@ int misc_init_r(void)
return 0;
}
int board_init(void)
{
return 0;
}
int board_late_init(void)
int qcom_late_init(void)
{
char serial[16];
@ -154,8 +109,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
{
u8 mac[ARP_HLEN];
msm_fixup_memory(blob);
if (!eth_env_get_enetaddr("wlanaddr", mac)) {
msm_generate_mac_addr(mac);
};
@ -177,8 +130,3 @@ int ft_board_setup(void *blob, struct bd_info *bd)
"local-bd-address", mac, ARP_HLEN, 1);
return 0;
}
void reset_cpu(void)
{
psci_system_reset();
}

15
board/qualcomm/dragonboard820c/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_DRAGONBOARD820C
config SYS_BOARD
default "dragonboard820c"
config SYS_VENDOR
default "qualcomm"
config SYS_SOC
default "apq8096"
config SYS_CONFIG_NAME
default "dragonboard820c"
endif

1
board/qualcomm/dragonboard820c/Makefile
View file

@ -3,4 +3,3 @@
# (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@gmail.com>
obj-y := dragonboard820c.o
extra-y += head.o

39
board/qualcomm/dragonboard820c/dragonboard820c.c
View file

@ -27,24 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
return 0;
}
static void sdhci_power_init(void)
{
const u32 TLMM_PULL_MASK = 0x3;
@ -113,28 +95,9 @@ static void sdhci_power_init(void)
rclk[i].val << rclk[i].bit);
}
static void show_psci_version(void)
{
struct arm_smccc_res res;
arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
printf("PSCI: v%ld.%ld\n",
PSCI_VERSION_MAJOR(res.a0),
PSCI_VERSION_MINOR(res.a0));
}
int board_init(void)
void qcom_board_init(void)
{
sdhci_power_init();
show_psci_version();
return 0;
}
void reset_cpu(void)
{
psci_system_reset();
}
/* Check for vol- button - if pressed - stop autoboot */

33
board/qualcomm/dragonboard820c/head.S
View file

@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ARM64 header for proper chain-loading with Little Kernel.
*
* Little Kernel shipped with Dragonboard820C boots standard Linux images for
* ARM64. This file adds header that is required to boot U-Boot properly.
*
* For details see:
* https://www.kernel.org/doc/Documentation/arm64/booting.txt
*
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
#include <config.h>
/*
* per document in linux/Doc/arm64/booting.text
*/
.global _arm64_header
_arm64_header:
b _start
.word 0
.quad CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
.quad 0 /* Effective size of kernel image, little-endian */
.quad 0 /* kernel flags, little-endian */
.quad 0 /* reserved */
.quad 0 /* reserved */
.quad 0 /* reserved */
.byte 0x41 /* Magic number, "ARM\x64" */
.byte 0x52
.byte 0x4d
.byte 0x64
.word 0 /* reserved (used for PE COFF offset) */

111
board/qualcomm/dragonboard820c/u-boot.lds
View file

@ -1,111 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Override linker script for fastboot-readable images
*
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*
* Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
*/
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_arm64_header)
SECTIONS
{
. = 0x00000000;
. = ALIGN(8);
.text :
{
*(.__image_copy_start)
board/qualcomm/dragonboard820c/head.o (.text*)
CPUDIR/start.o (.text*)
}
/* This needs to come before *(.text*) */
.efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
__efi_runtime_stop = .;
}
.text_rest :
{
*(.text*)
}
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(8);
.data : {
*(.data*)
}
. = ALIGN(8);
. = .;
. = ALIGN(8);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(8);
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
. = ALIGN(8);
.image_copy_end :
{
*(.__image_copy_end)
}
. = ALIGN(8);
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
.rela.dyn : {
*(.rela*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
}
_end = .;
. = ALIGN(8);
.bss_start : {
KEEP(*(.__bss_start));
}
.bss : {
*(.bss*)
. = ALIGN(8);
}
.bss_end : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

12
board/qualcomm/dragonboard845c/Kconfig
View file

@ -1,12 +0,0 @@
if TARGET_DRAGONBOARD845C
config SYS_BOARD
default "dragonboard845c"
config SYS_CONFIG_NAME
default "dragonboard845c"
config SYS_VENDOR
default "qualcomm"
endif

15
board/qualcomm/qcs404-evb/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_QCS404EVB
config SYS_BOARD
default "qcs404-evb"
config SYS_VENDOR
default "qualcomm"
config SYS_SOC
default "qcs404"
config SYS_CONFIG_NAME
default "qcs404-evb"
endif

6
board/qualcomm/qcs404-evb/Makefile
View file

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
#
obj-y += qcs404-evb.o

62
board/qualcomm/qcs404-evb/qcs404-evb.c
View file

@ -1,62 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board init file for QCS404-EVB
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
#include <init.h>
#include <asm/cache.h>
#include <asm/gpio.h>
#include <asm/global_data.h>
#include <fdt_support.h>
#include <asm/arch/dram.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int board_init(void)
{
struct udevice *pmic_gpio;
struct gpio_desc usb_vbus_boost_pin;
int ret, node;
ret = uclass_get_device_by_name(UCLASS_GPIO,
"pms405_gpios@c000",
&pmic_gpio);
if (ret < 0) {
printf("Failed to find pms405_gpios@c000 node.\n");
return ret;
}
node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
"usb_vbus_boost_pin");
if (node < 0) {
printf("Failed to find usb_hub_reset_pm dt node.\n");
return node;
}
ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
&usb_vbus_boost_pin, 0);
if (ret < 0) {
printf("Failed to request usb_hub_reset_pm gpio.\n");
return ret;
}
dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
return 0;
}
void reset_cpu(void)
{
psci_system_reset();
}

8
configs/dragonboard410c_defconfig
View file

@ -1,14 +1,15 @@
CONFIG_ARM=y
CONFIG_SYS_BOARD="dragonboard410c"
CONFIG_COUNTER_FREQUENCY=19000000
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_TEXT_BASE=0x8f600000
CONFIG_SYS_MALLOC_LEN=0x802000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
CONFIG_DEFAULT_DEVICE_TREE="apq8016-sbc"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_SYS_LOAD_ADDR=0x80080000
@ -38,7 +39,9 @@ CONFIG_CMD_TIMER=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_BUTTON_QCOM_PMIC=y
CONFIG_CLK=y
CONFIG_CLK_QCOM_APQ8016=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x91000000
CONFIG_FASTBOOT_FLASH=y
@ -52,6 +55,7 @@ CONFIG_MMC_SDHCI_MSM=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_QCOM_APQ8016=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_MSM_SERIAL=y

8
configs/dragonboard820c_defconfig
View file

@ -1,14 +1,13 @@
CONFIG_ARM=y
CONFIG_SYS_BOARD="dragonboard820c"
CONFIG_COUNTER_FREQUENCY=19000000
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x804000
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
CONFIG_TARGET_DRAGONBOARD820C=y
CONFIG_DEFAULT_DEVICE_TREE="apq8096-db820c"
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_DISTRO_DEFAULTS=y
@ -35,12 +34,15 @@ CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_EXT4_INTERFACE="mmc"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BUTTON_QCOM_PMIC=y
CONFIG_CLK=y
CONFIG_CLK_QCOM_APQ8096=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_QCOM_APQ8096=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_MSM_SERIAL=y

29
configs/dragonboard845c_defconfig
View file

@ -1,29 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=19000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
CONFIG_TARGET_DRAGONBOARD845C=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C"
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=5
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
CONFIG_SYS_CBSIZE=512
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_GPIO=y
# CONFIG_NET is not set
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_MSM_GENI_SERIAL=y
CONFIG_SPMI_MSM=y
CONFIG_LMB_MAX_REGIONS=64

67
configs/qcom_defconfig Normal file
View file

@ -0,0 +1,67 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_DEFAULT_DEVICE_TREE="sdm845-db845c"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BUTTON_CMD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTD_FULL=y
# CONFIG_BOOTMETH_VBE is not set
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
CONFIG_SYS_CBSIZE=512
CONFIG_LOG_MAX_LEVEL=9
CONFIG_LOG_DEFAULT_LEVEL=4
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_CAT=y
CONFIG_CMD_BMP=y
CONFIG_CMD_LOG=y
# CONFIG_NET is not set
CONFIG_BUTTON_QCOM_PMIC=y
CONFIG_CLK=y
CONFIG_CLK_QCOM_QCS404=y
CONFIG_CLK_QCOM_SDM845=y
CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_DM_KEYBOARD=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_QCOM_QCS404=y
CONFIG_PINCTRL_QCOM_SDM845=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_SCSI=y
CONFIG_MSM_SERIAL=y
CONFIG_MSM_GENI_SERIAL=y
CONFIG_SPMI_MSM=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_UFS=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_FONT_8X16 is not set
CONFIG_VIDEO_FONT_16X32=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
CONFIG_HEXDUMP=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set
CONFIG_LMB_MAX_REGIONS=64

55
configs/qcs404evb_defconfig
View file

@ -1,55 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=19000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
CONFIG_DM_RESET=y
CONFIG_TARGET_QCS404EVB=y
CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
CONFIG_SYS_CBSIZE=512
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_NET is not set
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_MISC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_PHY=y
CONFIG_PHY_QCOM_USB_HS_28NM=y
CONFIG_PHY_QCOM_USB_SS=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_MSM_SERIAL=y
CONFIG_SPMI_MSM=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_LMB_MAX_REGIONS=64

41
configs/starqltechn_defconfig
View file

@ -1,41 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=19000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_DEFAULT_DEVICE_TREE="starqltechn"
CONFIG_TARGET_STARQLTECHN=y
CONFIG_IDENT_STRING="\nSamsung S9 SM-G9600"
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=0
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_BMP=y
# CONFIG_NET is not set
CONFIG_BUTTON=y
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_DM_KEYBOARD=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_MSM_GENI_SERIAL=y
CONFIG_SPMI_MSM=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_FONT_8X16 is not set
CONFIG_VIDEO_FONT_16X32=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_SIMPLE=y
CONFIG_VIDEO_DT_SIMPLEFB=y
CONFIG_LMB_MAX_REGIONS=64

125
doc/board/qualcomm/board.rst Normal file
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@ -0,0 +1,125 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
Qualcomm generic boards
=======================
About this
----------
This document describes how to build and run U-Boot for Qualcomm generic
boards. Right now the generic target supports the Snapdragon 845 SoC, however
it's expected to support more SoCs going forward.
SDM845 - high-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
The current boot flow support loading u-boot as an Android boot image via
Qualcomm's UEFI-based ABL (Android) Bootloader. The DTB used by U-Boot will
be appended to the U-Boot image the same way as when booting Linux. U-Boot
will then retrieve the DTB during init. This way the memory layout and KASLR
offset will be populated by ABL.
Installation
------------
Build
^^^^^
$ ./tools/buildman/buildman -o .output qcom
This will build ``.output/u-boot-nodtb.bin`` using the ``qcom_defconfig``.
Generate FIT image (optional)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
See doc/uImage.FIT for more details
Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
We'll assemble android boot image with ``u-boot-nodtb.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
with appended dtb, so let's mimic linux to satisfy stock bootloader.
Boards
------
starqlte
^^^^^^^^
The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
based on the Qualcomm SDM845 SoC.
This device is supported by the common qcom_defconfig.
The DTB is called "sdm845-samsung-starqltechn.dtb"
More information can be found on the `Samsung S9 page`_.
dragonboard845c
^^^^^^^^^^^^^^^
The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
the Qualcomm SDM845 SoC.
This device is supported by the common qcom_defconfig
The DTB is called "sdm845-db845c.dtb"
More information can be found on the `DragonBoard 845c page`_.
qcs404-evb
^^^^^^^^^^
The QCS404 EvB is a Qualcomm Development Platform, based on the Qualcomm QCS404 SoC.
This device is supported by the common qcom_defconfig
The DTB is called "qcs404-evb-4000.dtb"
Building steps
--------------
Steps:
- Build u-boot
As above::
./tools/buildman/buildman -o .output qcom
Or for db410c (and other boards not supported by the generic target)::
make CROSS_COMPILE=aarch64-linux-gnu- O=.output dragonboard410c_defconfig
make O=.output -j$(nproc)
- gzip u-boot::
gzip u-boot-nodtb.bin
- Append dtb to gzipped u-boot::
cat u-boot-nodtb.bin.gz arch/arm/dts/your-board.dtb > u-boot-nodtb.bin.gz-dtb
- If you chose to build a FIT image, A ``qcom.its`` file can be found in ``board/qualcomm/generic/``
directory. It expects a folder as ``qcom_imgs/`` in the main directory containing pre-built kernel,
dts and ramdisk images. See ``qcom.its`` for full path to images::
mkimage -f qcom.its qcom.itb
- Now we've got everything to build android boot image::
mkbootimg --kernel u-boot-nodtb.bin.gz-dtb --ramdisk db845c.itb \
--output boot.img --pagesize 4096 --base 0x80000000
Or with no FIT image::
mkbootimg --kernel u-boot-nodtb.bin.gz-dtb \
--output boot.img --pagesize 4096 --base 0x80000000
- Flash boot.img using fastboot and erase dtbo to avoid conflicts with our DTB:
.. code-block:: bash
fastboot flash boot boot.img
fastboot erase dtbo
.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/

61
doc/board/qualcomm/debugging.rst Normal file
View file

@ -0,0 +1,61 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org>
Qualcomm debugging
==================
About this
----------
This page describes how to enable early UART and other debugging techniques
for Qualcomm boards.
Enable debug UART
-----------------
Newer boards (SDM845 and newer, those with GENI SE UART)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Open ``configs/qcom_defconfig`` and add the following snippet to the bottom:
CONFIG_BAUDRATE=115200
# Uncomment to enable UART pre-relocation
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ANNOUNCE=y
# This is the address of the debug-uart peripheral
# The value here is for SDM845, other platforms will vary
CONFIG_DEBUG_UART_BASE=0xa84000
# Boards older than ~2018 pre-date the GENI driver and unfortunately
# aren't supported here
CONFIG_DEBUG_UART_MSM_GENI=y
# For sdm845 this is the UART clock rate
CONFIG_DEBUG_UART_CLOCK=7372800
# Most newer boards have an oversampling value of 16 instead
# of 32, they need the clock rate to be doubled
#CONFIG_DEBUG_UART_CLOCK=14745600
Then build as normal (don't forget to ``make qcom_defconfig``` again).
Older boards (db410c and db820c)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Open ``configs/dragonboard<BOARD>_defconfig``
CONFIG_BAUDRATE=115200
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ANNOUNCE=y
# db410c - 0x78b0000
# db820c - 0x75b0000
CONFIG_DEBUG_UART_BASE=0x75b0000
CONFIG_DEBUG_UART_MSM=y
CONFIG_DEBUG_UART_CLOCK=7372800
#CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_LOG=y
CONFIG_HEXDUMP=y
CONFIG_CMD_LOG=y
CONFIG_LOG_MAX_LEVEL=9
CONFIG_LOG_DEFAULT_LEVEL=9
CONFIG_LOGLEVEL=9

2
doc/board/qualcomm/dragonboard410c.rst
View file

@ -14,6 +14,8 @@ through LK. This is no longer the case, now U-Boot can replace LK entirely.
.. _96Boards product page: https://www.96boards.org/product/dragonboard410c/
.. _MSM8916/SD410/APQ8016 Technical Reference Manual: https://web.archive.org/web/20210525022203/https://developer.qualcomm.com/qfile/35259/lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf
Installation
------------
First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``dragonboard410c``::

4
doc/board/qualcomm/index.rst
View file

@ -7,5 +7,5 @@ Qualcomm
:maxdepth: 2
dragonboard410c
sdm845
qcs404
board
debugging

79
doc/board/qualcomm/qcs404.rst
View file

@ -1,79 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Sumit Garg <sumit.garg@linaro.org>
QCS404 EVB
==========
About this
----------
This document describes the information about Qualcomm QCS404 evaluation board
and it's usage steps.
The current boot flow support loading u-boot as an Android boot image via
Qualcomm's UEFI-based ABL (Android) Bootloader.
Installation
------------
Build
^^^^^
Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make qcs404evb_defconfig
$ make
This will build ``u-boot.bin`` in the configured output directory.
Generate FIT image
^^^^^^^^^^^^^^^^^^
A ``qcs404.its`` file can be found in ``board/qualcomm/qcs404-evb/`` directory.
It expects a folder as ``qcs404_imgs/`` in the main directory containing
pre-built kernel, dts and ramdisk images. See ``qcs404.its`` for full path to
images.
- Build FIT image::
mkimage -f qcs404-evb.its qcs404-evb.itb
Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
with appended dtb, so let's mimic linux to satisfy stock bootloader:
- create dump dtb::
workdir=/tmp/prepare_payload
mkdir -p "$workdir"
cd "$workdir"
mock_dtb="$workdir"/payload_mock.dtb
dtc -I dts -O dtb -o "$mock_dtb" << EOF
/dts-v1/;
/ {
model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", "qcom,qcs404";
#address-cells = <2>;
#size-cells = <2>;
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
chosen { };
};
EOF
- gzip u-boot ``gzip u-boot.bin``
- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
Now we've got everything to build android boot image:::
mkbootimg --kernel u-boot.bin.gz-dtb \
--ramdisk qcs404-evb.itb --pagesize 4096 \
--base 0x80000000 --output boot.img
Flash image on qcs404-evb using fastboot method.

167
doc/board/qualcomm/sdm845.rst
View file

@ -1,167 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
Snapdragon 845
==============
About this
----------
This document describes the information about Qualcomm Snapdragon 845
supported boards and it's usage steps.
SDM845 - hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
The current boot flow support loading u-boot as an Android boot image via
Qualcomm's UEFI-based ABL (Android) Bootloader.
Installation
------------
Build
^^^^^
Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make <your board name here, see Boards section>_defconfig
$ make
This will build ``u-boot.bin`` in the configured output directory.
Generate FIT image
^^^^^^^^^^^^^^^^^^
See doc/uImage.FIT for more details
Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
with appended dtb, so let's mimic linux to satisfy stock bootloader.
Boards
------
starqlte
^^^^^^^^
The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
based on the Qualcomm SDM845 SoC.
Steps:
- Build u-boot::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make starqltechn_defconfig
$ make
- Create dump dtb::
workdir=/tmp/prepare_payload
mkdir -p "$workdir"
cd "$workdir"
mock_dtb="$workdir"/payload_mock.dtb
dtc -I dts -O dtb -o "$mock_dtb" << EOF
/dts-v1/;
/ {
memory {
/* We expect the bootloader to fill in the size */
reg = <0 0 0 0>;
};
chosen { };
};
EOF
- gzip u-boot::
gzip u-boot.bin
- Append dtb to gzipped u-boot::
cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
- Now we've got everything to build android boot image::
mkbootimg --base 0x0 --kernel_offset 0x00008000 \
--ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \
--pagesize 4096 --second_offset 0x00f00000 \
--ramdisk "$fit_image" \
--kernel u-boot.bin.gz-dtb \
-o boot.img
- Flash image with your phone's flashing method.
More information can be found on the `Samsung S9 page`_.
dragonboard845c
^^^^^^^^^^^^^^^
The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
the Qualcomm SDM845 SoC.
Steps:
- Build u-boot::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make dragonboard845c_defconfig
$ make
- Create dummy dtb::
workdir=/tmp/prepare_payload
mkdir -p "$workdir"
mock_dtb="$workdir"/payload_mock.dtb
dtc -I dts -O dtb -o "$mock_dtb" << EOF
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
chosen { };
};
EOF
- gzip u-boot::
gzip u-boot.bin
- Append dtb to gzipped u-boot::
cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
- A ``db845c.its`` file can be found in ``board/qualcomm/dragonboard845c/``
directory. It expects a folder as ``db845c_imgs/`` in the main directory
containing pre-built kernel, dts and ramdisk images. See ``db845c.its``
for full path to images::
mkimage -f db845c.its db845c.itb
- Now we've got everything to build android boot image::
mkbootimg --kernel u-boot.bin.gz-dtb --ramdisk db845c.itb \
--output boot.img --pagesize 4096 --base 0x80000000
- Flash boot.img using db845c fastboot method:
.. code-block:: bash
sudo fastboot flash boot boot.img
More information can be found on the `DragonBoard 845c page`_.
.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/

25
doc/device-tree-bindings/mmc/msm_sdhci.txt
View file

@ -1,25 +0,0 @@
Qualcomm Snapdragon SDHCI controller
Required properties:
- compatible : "qcom,sdhci-msm-v4"
- reg: Base address and length of registers:
- Host controller registers (SDHCI)
- SD Core registers
- clock: interface clock (must accept SD bus clock as a frequency)
Optional properties:
- index: If there is more than one controller - controller index (required
by generic SDHCI code).
- bus_width: Width of SD/eMMC bus (default 4)
- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
Example:
sdhci@07864000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7864900 0x11c 0x7864000 0x800>;
index = <0x1>;
bus-width = <0x4>;
clock = <&clkc 1>;
clock-frequency = <200000000>;
};

10
doc/device-tree-bindings/usb/ehci-msm.txt
View file

@ -1,10 +0,0 @@
Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices.
Required properties:
- compatible: must be "qcom,ehci-host"
- reg: start address and size of the registers
ehci@78d9000 {
compatible = "qcom,ehci-host";
reg = <0x78d9000 0x400>;
};

21
drivers/clk/qcom/clock-apq8016.c
View file

@ -13,6 +13,7 @@
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include "clock-qcom.h"
@ -102,20 +103,20 @@ static const struct bcr_regs uart2_regs = {
};
/* UART: 115200 */
static int clk_init_uart(struct msm_clk_priv *priv)
int apq8016_clk_init_uart(phys_addr_t base)
{
/* Enable AHB clock */
clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_gpll0(base, &gpll0_vote_clk);
/* Enable core clk */
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR);
return 0;
}
@ -125,14 +126,14 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case 0: /* SDC1 */
case GCC_SDCC1_APPS_CLK: /* SDC1 */
return clk_init_sdc(priv, 0, rate);
break;
case 1: /* SDC2 */
case GCC_SDCC2_APPS_CLK: /* SDC2 */
return clk_init_sdc(priv, 1, rate);
break;
case 4: /* UART2 */
return clk_init_uart(priv);
case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
return apq8016_clk_init_uart(priv->base);
break;
default:
return 0;
@ -145,7 +146,7 @@ static struct msm_clk_data apq8016_clk_data = {
static const struct udevice_id gcc_apq8016_of_match[] = {
{
.compatible = "qcom,gcc-apq8016",
.compatible = "qcom,gcc-msm8916",
.data = (ulong)&apq8016_clk_data,
},
{ }

7
drivers/clk/qcom/clock-apq8096.c
View file

@ -13,6 +13,7 @@
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include "clock-qcom.h"
@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case 0: /* SDC1 */
case GCC_SDCC1_APPS_CLK: /* SDC1 */
return clk_init_sdc(priv, rate);
break;
case 4: /*UART2*/
case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
return clk_init_uart(priv);
default:
return 0;
@ -123,7 +124,7 @@ static struct msm_clk_data apq8096_clk_data = {
static const struct udevice_id gcc_apq8096_of_match[] = {
{
.compatible = "qcom,gcc-apq8096",
.compatible = "qcom,gcc-msm8996",
.data = (ulong)&apq8096_clk_data,
},
{ }

25
drivers/clk/qcom/clock-qcs404.c
View file

@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
switch (clk->id) {
case GCC_BLSP1_UART2_APPS_CLK:
/* UART: 115200 */
/* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
CFG_CLK_SRC_CXO, 16);
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
break;
case GCC_BLSP1_AHB_CLK:
clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
break;
return 1843200;
case GCC_SDCC1_APPS_CLK:
/* SDCC1: 200MHz */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
break;
case GCC_SDCC1_AHB_CLK:
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
break;
return rate;
case GCC_ETH_RGMII_CLK:
if (rate == 250000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
else if (rate == 5000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
CFG_CLK_SRC_GPLL1, 8);
break;
default:
return 0;
return rate;
}
/* There is a bug only seeming to affect this board where the MMC driver somehow calls
* clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
* The only clock with ID 0 is the xo_board clock which should not be associated with
* this device...
*/
log_debug("Unknown clock id %ld\n", clk->id);
return 0;
}
@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk)
clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_SDCC1_AHB_CLK:
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
break;
default:
return 0;
}

20
drivers/gpio/msm_gpio.c
View file

@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
return 0;
/* Disable OE bit */
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
GPIO_OE_MASK, GPIO_OE_DISABLE);
@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
return 0;
value = !!value;
/* set value */
writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
return 0;
value = !!value;
/* set value */
writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
return 0;
return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
}
@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
return 0;
if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
return GPIOF_OUTPUT;

277
drivers/gpio/qcom_pmic_gpio.c
View file

@ -7,10 +7,14 @@
#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <log.h>
#include <power/pmic.h>
#include <spmi/spmi.h>
#include <asm/io.h>
#include <stdlib.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
@ -64,27 +68,34 @@
#define REG_EN_CTL 0x46
#define REG_EN_CTL_ENABLE (1 << 7)
struct qcom_gpio_bank {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
/**
* pmic_gpio_match_data - platform specific configuration
*
* @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them.
* This is a workaround for an unknown bug on some platforms where trying to write the
* GPIO configuration registers causes the board to hang.
*/
enum pmic_gpio_quirks {
QCOM_PMIC_QUIRK_READONLY = (1 << 0),
};
static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
bool input, int value)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
uint32_t reg_ctl_val;
int ret;
struct qcom_pmic_gpio_data {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
u32 pin_count;
struct udevice *pmic; /* Reference to pmic device for read/write */
};
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
REG_EN_CTL_ENABLE, 0);
if (ret < 0)
return ret;
/* dev can be the GPIO or pinctrl device */
static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool input, int value)
{
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
u32 gpio_base = plat->pid + REG_OFFSET(offset);
u32 reg_ctl_val;
int ret = 0;
/* Select the mode and output */
if (priv->lv_mv_type) {
if (plat->lv_mv_type) {
if (input)
reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
else
@ -96,20 +107,43 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
}
ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val);
ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
if (ret < 0)
return ret;
if (priv->lv_mv_type && !input) {
ret = pmic_reg_write(dev->parent,
if (plat->lv_mv_type && !input) {
ret = pmic_reg_write(plat->pmic,
gpio_base + REG_LV_MV_OUTPUT_CTL,
!!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
if (ret < 0)
return ret;
}
return 0;
}
static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
bool input, int value)
{
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
ulong quirks = dev_get_driver_data(dev);
int ret = 0;
/* Some PMICs don't like their GPIOs being configured */
if (quirks & QCOM_PMIC_QUIRK_READONLY)
return 0;
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
REG_EN_CTL_ENABLE, 0);
if (ret < 0)
return ret;
_qcom_gpio_set_direction(dev, offset, input, value);
/* Set the right pull (no pull) */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
REG_DIG_PULL_NO_PU);
if (ret < 0)
return ret;
@ -117,13 +151,13 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
/* Configure output pin drivers if needed */
if (!input) {
/* Select the VIN - VIN0, pin is input so it doesn't matter */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
REG_DIG_VIN_VIN0);
if (ret < 0)
return ret;
/* Set the right dig out control */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_OUT_CTL,
REG_DIG_OUT_CTL_CMOS |
REG_DIG_OUT_CTL_DRIVE_L);
if (ret < 0)
@ -148,15 +182,15 @@ static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset,
static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
int reg;
reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);
reg = pmic_reg_read(plat->pmic, gpio_base + REG_CTL);
if (reg < 0)
return reg;
if (priv->lv_mv_type) {
if (plat->lv_mv_type) {
switch (reg & REG_CTL_LV_MV_MODE_MASK) {
case REG_CTL_LV_MV_MODE_INPUT:
return GPIOF_INPUT;
@ -181,11 +215,11 @@ static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
int reg;
reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
reg = pmic_reg_read(plat->pmic, gpio_base + REG_STATUS);
if (reg < 0)
return reg;
@ -195,11 +229,11 @@ static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
/* Set the output value of the gpio */
if (priv->lv_mv_type)
if (plat->lv_mv_type)
return pmic_clrsetbits(dev->parent,
gpio_base + REG_LV_MV_OUTPUT_CTL,
REG_LV_MV_OUTPUT_CTL_MASK,
@ -209,71 +243,104 @@ static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
REG_CTL_OUTPUT_MASK, !!value);
}
static int qcom_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
struct ofnode_phandle_args *args)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (args->args_count < 1)
return -EINVAL;
/* GPIOs in DT are 1-based */
desc->offset = args->args[0] - 1;
if (desc->offset >= uc_priv->gpio_count)
return -EINVAL;
if (args->args_count < 2)
return 0;
desc->flags = gpio_flags_xlate(args->args[1]);
return 0;
}
static const struct dm_gpio_ops qcom_gpio_ops = {
.direction_input = qcom_gpio_direction_input,
.direction_output = qcom_gpio_direction_output,
.get_value = qcom_gpio_get_value,
.set_value = qcom_gpio_set_value,
.get_function = qcom_gpio_get_function,
.xlate = qcom_gpio_xlate,
};
static int qcom_gpio_bind(struct udevice *dev)
{
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
ulong quirks = dev_get_driver_data(dev);
struct udevice *child;
struct driver *drv;
int ret;
drv = lists_driver_lookup_name("qcom_pmic_pinctrl");
if (!drv) {
log_warning("Cannot find driver '%s'\n", "qcom_pmic_pinctrl");
return -ENOENT;
}
/* Bind the GPIO driver as a child of the PMIC. */
ret = device_bind_with_driver_data(dev, drv,
dev->name,
quirks, dev_ofnode(dev), &child);
if (ret)
return log_msg_ret("bind", ret);
dev_set_plat(child, plat);
return 0;
}
static int qcom_gpio_probe(struct udevice *dev)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
int reg;
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
struct ofnode_phandle_args args;
int val, ret;
u64 pid;
plat->pmic = dev->parent;
pid = dev_read_addr(dev);
if (pid == FDT_ADDR_T_NONE)
return log_msg_ret("bad address", -EINVAL);
priv->pid = pid;
plat->pid = pid;
/* Do a sanity check */
reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
if (reg != REG_TYPE_VAL)
val = pmic_reg_read(plat->pmic, plat->pid + REG_TYPE);
if (val != REG_TYPE_VAL)
return log_msg_ret("bad type", -ENXIO);
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
if (reg != REG_SUBTYPE_GPIO_4CH && reg != REG_SUBTYPE_GPIOC_4CH &&
reg != REG_SUBTYPE_GPIO_LV && reg != REG_SUBTYPE_GPIO_MV)
val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&
val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
return log_msg_ret("bad subtype", -ENXIO);
priv->lv_mv_type = reg == REG_SUBTYPE_GPIO_LV ||
reg == REG_SUBTYPE_GPIO_MV;
return 0;
}
/*
* Parse basic GPIO count specified via the gpio-ranges property
* as specified in Linux devicetrees
* Returns < 0 on error, otherwise gpio count
*/
static int qcom_gpio_of_parse_ranges(struct udevice *dev)
{
int ret;
struct ofnode_phandle_args args;
plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
val == REG_SUBTYPE_GPIO_MV;
/*
* Parse basic GPIO count specified via the gpio-ranges property
* as specified in upstream devicetrees
*/
ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
NULL, 3, 0, &args);
if (ret)
return log_msg_ret("gpio-ranges", ret);
return args.args[2];
}
static int qcom_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
ret = qcom_gpio_of_parse_ranges(dev);
if (ret > 0)
uc_priv->gpio_count = ret;
else
return ret;
plat->pin_count = args.args[2];
uc_priv->gpio_count = plat->pin_count;
uc_priv->bank_name = "pmic";
return 0;
@ -282,7 +349,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
{ .compatible = "qcom,pm8998-gpio" },
{ .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ .compatible = "qcom,pms405-gpio" },
{ }
};
@ -291,9 +358,75 @@ U_BOOT_DRIVER(qcom_pmic_gpio) = {
.name = "qcom_pmic_gpio",
.id = UCLASS_GPIO,
.of_match = qcom_gpio_ids,
.of_to_plat = qcom_gpio_of_to_plat,
.probe = qcom_gpio_probe,
.bind = qcom_gpio_bind,
.probe = qcom_gpio_probe,
.ops = &qcom_gpio_ops,
.priv_auto = sizeof(struct qcom_gpio_bank),
.plat_auto = sizeof(struct qcom_pmic_gpio_data),
.flags = DM_FLAG_ALLOC_PDATA,
};
static const struct pinconf_param qcom_pmic_pinctrl_conf_params[] = {
{ "output-high", PIN_CONFIG_OUTPUT_ENABLE, 1 },
{ "output-low", PIN_CONFIG_OUTPUT, 0 },
};
static int qcom_pmic_pinctrl_get_pins_count(struct udevice *dev)
{
struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
return plat->pin_count;
}
static const char *qcom_pmic_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector)
{
static char name[8];
/* DT indexes from 1 */
snprintf(name, sizeof(name), "gpio%u", selector + 1);
return name;
}
static int qcom_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector,
unsigned int param, unsigned int arg)
{
/* We only support configuring the pin as an output, either low or high */
return _qcom_gpio_set_direction(dev, selector, false,
param == PIN_CONFIG_OUTPUT_ENABLE);
}
static const char *qcom_pmic_pinctrl_get_function_name(struct udevice *dev, unsigned int selector)
{
if (!selector)
return "normal";
return NULL;
}
static int qcom_pmic_pinctrl_generic_get_functions_count(struct udevice *dev)
{
return 1;
}
static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigned int selector,
unsigned int func_selector)
{
return 0;
}
struct pinctrl_ops qcom_pmic_pinctrl_ops = {
.get_pins_count = qcom_pmic_pinctrl_get_pins_count,
.get_pin_name = qcom_pmic_pinctrl_get_pin_name,
.set_state = pinctrl_generic_set_state,
.pinconf_num_params = ARRAY_SIZE(qcom_pmic_pinctrl_conf_params),
.pinconf_params = qcom_pmic_pinctrl_conf_params,
.pinconf_set = qcom_pmic_pinctrl_pinconf_set,
.get_function_name = qcom_pmic_pinctrl_get_function_name,
.get_functions_count = qcom_pmic_pinctrl_generic_get_functions_count,
.pinmux_set = qcom_pmic_pinctrl_generic_pinmux_set_mux,
};
U_BOOT_DRIVER(qcom_pmic_pinctrl) = {
.name = "qcom_pmic_pinctrl",
.id = UCLASS_PINCTRL,
.ops = &qcom_pmic_pinctrl_ops,
};

69
drivers/mmc/msm_sdhci.c
View file

@ -44,6 +44,7 @@ struct msm_sdhc_plat {
struct msm_sdhc {
struct sdhci_host host;
void *base;
struct clk_bulk clks;
};
struct msm_sdhc_variant_info {
@ -54,35 +55,57 @@ DECLARE_GLOBAL_DATA_PTR;
static int msm_sdc_clk_init(struct udevice *dev)
{
int node = dev_of_offset(dev);
uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
400000);
uint clkd[2]; /* clk_id and clk_no */
int clk_offset;
struct udevice *clk_dev;
struct clk clk;
int ret;
struct msm_sdhc *prv = dev_get_priv(dev);
ofnode node = dev_ofnode(dev);
ulong clk_rate;
int ret, i = 0, n_clks;
const char *clk_name;
ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate));
if (ret)
return ret;
clk_rate = 400000;
clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
if (clk_offset < 0)
return clk_offset;
ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
if (ret)
ret = clk_get_bulk(dev, &prv->clks);
if (ret) {
log_warning("Couldn't get mmc clocks: %d\n", ret);
return ret;
}
clk.id = clkd[1];
ret = clk_request(clk_dev, &clk);
if (ret < 0)
ret = clk_enable_bulk(&prv->clks);
if (ret) {
log_warning("Couldn't enable mmc clocks: %d\n", ret);
return ret;
}
ret = clk_set_rate(&clk, clk_rate);
if (ret < 0)
return ret;
/* If clock-names is unspecified, then the first clock is the core clock */
if (!ofnode_get_property(node, "clock-names", &n_clks)) {
if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
log_warning("Couldn't set core clock rate: %d\n", ret);
return -EINVAL;
}
}
/* Find the index of the "core" clock */
while (i < n_clks) {
ofnode_read_string_index(node, "clock-names", i, &clk_name);
if (!strcmp(clk_name, "core"))
break;
i++;
}
if (i >= prv->clks.count) {
log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
prv->clks.count);
return -EINVAL;
}
/* The clock is already enabled by the clk_bulk above */
clk_rate = clk_set_rate(&prv->clks.clks[i], clk_rate);
/* If we get a rate of 0 then something has probably gone wrong. */
if (clk_rate == 0 || IS_ERR((void *)clk_rate)) {
log_warning("Couldn't set MMC core clock rate: %dE\n", clk_rate ? (int)PTR_ERR((void *)clk_rate) : 0);
return -EINVAL;
}
return 0;
}
@ -187,6 +210,8 @@ static int msm_sdc_remove(struct udevice *dev)
if (!var_info->mci_removed)
writel(0, priv->base + SDCC_MCI_HC_MODE);
clk_release_bulk(&priv->clks);
return 0;
}

4
drivers/phy/qcom/msm8916-usbh-phy.c
View file

@ -74,7 +74,7 @@ static int msm_phy_probe(struct udevice *dev)
{
struct msm_phy_priv *priv = dev_get_priv(dev);
priv->regs = dev_remap_addr(dev);
priv->regs = dev_remap_addr(dev_get_parent(dev));
if (!priv->regs)
return -EINVAL;
@ -96,7 +96,7 @@ static struct phy_ops msm_phy_ops = {
};
static const struct udevice_id msm_phy_ids[] = {
{ .compatible = "qcom,apq8016-usbphy" },
{ .compatible = "qcom,usb-hs-phy-msm8916" },
{ }
};

34
drivers/pinctrl/qcom/pinctrl-apq8016.c
View file

@ -14,22 +14,22 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
"SDC1_CLK",
"SDC1_CMD",
"SDC1_DATA",
"SDC2_CLK",
"SDC2_CMD",
"SDC2_DATA",
"QDSD_CLK",
"QDSD_CMD",
"QDSD_DATA0",
"QDSD_DATA1",
"QDSD_DATA2",
"QDSD_DATA3",
"sdc1_clk",
"sdc1_cmd",
"sdc1_data",
"sdc2_clk",
"sdc2_cmd",
"sdc2_data",
"qdsd_clk",
"qdsd_cmd",
"qdsd_data0",
"qdsd_data1",
"qdsd_data2",
"qdsd_data3",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
{"blsp1_uart", 2},
{"blsp_uart2", 2},
};
static const char *apq8016_get_function_name(struct udevice *dev,
@ -42,7 +42,7 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 122) {
snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 122];
@ -55,7 +55,10 @@ static unsigned int apq8016_get_function_mux(unsigned int selector)
}
static const struct msm_pinctrl_data apq8016_data = {
.pin_data = { .pin_count = 133, },
.pin_data = {
.pin_count = 133,
.special_pins_start = 122,
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = apq8016_get_function_name,
.get_function_mux = apq8016_get_function_mux,
@ -73,4 +76,5 @@ U_BOOT_DRIVER(pinctrl_apq8016) = {
.of_match = msm_pinctrl_ids,
.ops = &msm_pinctrl_ops,
.bind = msm_pinctrl_bind,
.flags = DM_FLAG_PRE_RELOC,
};

21
drivers/pinctrl/qcom/pinctrl-apq8096.c
View file

@ -14,13 +14,13 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
"SDC1_CLK",
"SDC1_CMD",
"SDC1_DATA",
"SDC2_CLK",
"SDC2_CMD",
"SDC2_DATA",
"SDC1_RCLK",
"sdc1_clk",
"sdc1_cmd",
"sdc1_data",
"sdc2_clk",
"sdc2_cmd",
"sdc2_data",
"sdc1_rclk",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
@ -37,7 +37,7 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 150) {
snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 150];
@ -50,7 +50,10 @@ static unsigned int apq8096_get_function_mux(unsigned int selector)
}
static const struct msm_pinctrl_data apq8096_data = {
.pin_data = { .pin_count = 157, },
.pin_data = {
.pin_count = 157,
.special_pins_start = 150,
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = apq8096_get_function_name,
.get_function_mux = apq8096_get_function_mux,

5
drivers/pinctrl/qcom/pinctrl-ipq4019.c
View file

@ -46,7 +46,10 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector)
}
static const struct msm_pinctrl_data ipq4019_data = {
.pin_data = { .pin_count = 100, },
.pin_data = {
.pin_count = 100,
.special_pins_start = 100, /* There are no special pins */
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = ipq4019_get_function_name,
.get_function_mux = ipq4019_get_function_mux,

12
drivers/pinctrl/qcom/pinctrl-qcom.c
View file

@ -16,6 +16,7 @@
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include <linux/bug.h>
#include <mach/gpio.h>
#include "pinctrl-qcom.h"
@ -83,6 +84,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
priv->data->get_function_mux(func_selector) << 2);
@ -94,6 +99,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
/* Always NOP for special pins */
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
return 0;
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
argument = (argument / 2) - 1;
@ -136,6 +145,9 @@ int msm_pinctrl_bind(struct udevice *dev)
const char *name;
int ret;
if (!data->pin_data.special_pins_start)
dev_warn(dev, "Special pins start index not defined!\n");
drv = lists_driver_lookup_name("pinctrl_qcom");
if (!drv)
return -ENOENT;

64
drivers/pinctrl/qcom/pinctrl-qcs404.c
View file

@ -10,20 +10,24 @@
#include "pinctrl-qcom.h"
#define NORTH 0x00300000
#define SOUTH 0x00000000
#define EAST 0x06b00000
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
"SDC1_RCLK",
"SDC1_CLK",
"SDC1_CMD",
"SDC1_DATA",
"SDC2_CLK",
"SDC2_CMD",
"SDC2_DATA",
"sdc1_rclk",
"sdc1_clk",
"sdc1_cmd",
"sdc1_data",
"sdc2_clk",
"sdc2_cmd",
"sdc2_data",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
{"blsp_uart2", 1},
{"gpio", 0},
{"rgmii_int", 1},
{"rgmii_ck", 1},
{"rgmii_tx", 1},
@ -37,6 +41,40 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
{"blsp_i2c_scl_a2", 3},
{"blsp_i2c3", 2},
{"blsp_i2c4", 1},
{"blsp_uart_tx_a2", 1},
{"blsp_uart_rx_a2", 1},
};
static const unsigned int qcs404_pin_offsets[] = {
[0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, [4] = SOUTH,
[5] = SOUTH, [6] = SOUTH, [7] = SOUTH, [8] = SOUTH, [9] = SOUTH,
[10] = SOUTH, [11] = SOUTH, [12] = SOUTH, [13] = SOUTH, [14] = SOUTH,
[15] = SOUTH, [16] = SOUTH, [17] = NORTH, [18] = NORTH, [19] = NORTH,
[20] = NORTH, [21] = SOUTH, [22] = NORTH, [23] = NORTH, [24] = NORTH,
[25] = NORTH, [26] = EAST, [27] = EAST, [28] = EAST, [29] = EAST,
[30] = NORTH, [31] = NORTH, [32] = NORTH, [33] = NORTH, [34] = SOUTH,
[35] = SOUTH, [36] = NORTH, [37] = NORTH, [38] = NORTH, [39] = EAST,
[40] = EAST, [41] = EAST, [42] = EAST, [43] = EAST, [44] = EAST,
[45] = EAST, [46] = EAST, [47] = EAST, [48] = EAST, [49] = EAST,
[50] = EAST, [51] = EAST, [52] = EAST, [53] = EAST, [54] = EAST,
[55] = EAST, [56] = EAST, [57] = EAST, [58] = EAST, [59] = EAST,
[60] = NORTH, [61] = NORTH, [62] = NORTH, [63] = NORTH, [64] = NORTH,
[65] = NORTH, [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = NORTH,
[70] = NORTH, [71] = NORTH, [72] = NORTH, [73] = NORTH, [74] = NORTH,
[75] = NORTH, [76] = NORTH, [77] = NORTH, [78] = EAST, [79] = EAST,
[80] = EAST, [81] = EAST, [82] = NORTH, [83] = NORTH, [84] = NORTH,
[85] = NORTH, [86] = EAST, [87] = EAST, [88] = EAST, [89] = EAST,
[90] = EAST, [91] = EAST, [92] = EAST, [93] = EAST, [94] = EAST,
[95] = EAST, [96] = EAST, [97] = EAST, [98] = EAST, [99] = EAST,
[100] = EAST, [101] = EAST, [102] = EAST, [103] = EAST, [104] = EAST,
[105] = EAST, [106] = EAST, [107] = EAST, [108] = EAST, [109] = EAST,
[110] = EAST, [111] = EAST, [112] = EAST, [113] = EAST, [114] = EAST,
[115] = EAST, [116] = EAST, [117] = NORTH, [118] = NORTH, [119] = EAST,
/*
* There's 126 pins but the last ones are special and have non-standard registers
* so we leave them out here. The pinctrl and GPIO drivers both currently ignore
* these pins.
*/
};
static const char *qcs404_get_function_name(struct udevice *dev,
@ -49,7 +87,7 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 120) {
snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 120];
@ -61,8 +99,12 @@ static unsigned int qcs404_get_function_mux(unsigned int selector)
return msm_pinctrl_functions[selector].val;
}
static struct msm_pinctrl_data qcs404_data = {
.pin_data = { .pin_count = 126, },
static const struct msm_pinctrl_data qcs404_data = {
.pin_data = {
.pin_count = 126,
.pin_offsets = qcs404_pin_offsets,
.special_pins_start = 120,
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = qcs404_get_function_name,
.get_function_mux = qcs404_get_function_mux,

5
drivers/pinctrl/qcom/pinctrl-sdm845.c
View file

@ -75,10 +75,11 @@ static unsigned int sdm845_get_function_mux(unsigned int selector)
return msm_pinctrl_functions[selector].val;
}
static struct msm_pinctrl_data sdm845_data = {
static const struct msm_pinctrl_data sdm845_data = {
.pin_data = {
.pin_offsets = sdm845_pin_offsets,
.pin_count = ARRAY_SIZE(sdm845_pin_offsets),
.pin_count = 154,
.special_pins_start = 150,
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = sdm845_get_function_name,

8
drivers/serial/Kconfig
View file

@ -319,6 +319,14 @@ config DEBUG_UART_S5P
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
config DEBUG_UART_MSM
bool "Qualcomm QUP UART debug"
depends on ARCH_SNAPDRAGON
help
Select this to enable a debug UART using the serial_msm driver. You
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
config DEBUG_UART_MSM_GENI
bool "Qualcomm snapdragon"
depends on ARCH_SNAPDRAGON

62
drivers/serial/serial_msm.c
View file

@ -160,29 +160,14 @@ static int msm_uart_clk_init(struct udevice *dev)
{
uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 115200);
uint clkd[2]; /* clk_id and clk_no */
int clk_offset;
struct udevice *clk_dev;
struct clk clk;
int ret;
ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
clkd, 2);
if (ret)
return ret;
clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
if (clk_offset < 0)
return clk_offset;
ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
if (ret)
return ret;
clk.id = clkd[1];
ret = clk_request(clk_dev, &clk);
if (ret < 0)
ret = clk_get_by_name(dev, "core", &clk);
if (ret < 0) {
pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
return ret;
}
ret = clk_set_rate(&clk, clk_rate);
if (ret < 0)
@ -218,7 +203,6 @@ static int msm_serial_probe(struct udevice *dev)
if (ret)
return ret;
pinctrl_select_state(dev, "uart");
uart_dm_init(priv);
return 0;
@ -251,4 +235,42 @@ U_BOOT_DRIVER(serial_msm) = {
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops = &msm_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_MSM
static struct msm_serial_data init_serial_data = {
.base = CONFIG_VAL(DEBUG_UART_BASE),
.clk_rate = 7372800,
};
#include <debug_uart.h>
/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
//int apq8016_clk_init_uart(phys_addr_t gcc_base);
static inline void _debug_uart_init(void)
{
/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
//apq8016_clk_init_uart(0x1800000);
uart_dm_init(&init_serial_data);
}
static inline void _debug_uart_putc(int ch)
{
struct msm_serial_data *priv = &init_serial_data;
while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
!(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
;
writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
writel(1, priv->base + UARTDM_NCF_TX);
writel(ch, priv->base + UARTDM_TF);
}
DEBUG_UART_FUNCS
#endif

24
drivers/usb/dwc3/dwc3-generic.c
View file

@ -21,6 +21,7 @@
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
#include <power/regulator.h>
#include <usb.h>
#include "core.h"
#include "gadget.h"
@ -47,6 +48,7 @@ struct dwc3_generic_priv {
struct dwc3_generic_host_priv {
struct xhci_ctrl xhci_ctrl;
struct dwc3_generic_priv gen_priv;
struct udevice *vbus_supply;
};
static int dwc3_generic_probe(struct udevice *dev,
@ -240,11 +242,24 @@ static int dwc3_generic_host_probe(struct udevice *dev)
if (rc)
return rc;
rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply);
if (rc)
debug("%s: No vbus regulator found: %d\n", dev->name, rc);
/* Only returns an error if regulator is valid and failed to enable due to a driver issue */
rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
if (rc)
return rc;
hccr = (struct xhci_hccr *)priv->gen_priv.base;
hcor = (struct xhci_hcor *)(priv->gen_priv.base +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
return xhci_register(dev, hccr, hcor);
rc = xhci_register(dev, hccr, hcor);
if (rc)
regulator_set_enable_if_allowed(priv->vbus_supply, false);
return rc;
}
static int dwc3_generic_host_remove(struct udevice *dev)
@ -252,9 +267,12 @@ static int dwc3_generic_host_remove(struct udevice *dev)
struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
int rc;
rc = xhci_deregister(dev);
/* This function always returns 0 */
xhci_deregister(dev);
rc = regulator_set_enable_if_allowed(priv->vbus_supply, false);
if (rc)
return rc;
debug("%s: Failed to disable vbus regulator: %d\n", dev->name, rc);
return dwc3_generic_remove(dev, &priv->gen_priv);
}

22
drivers/usb/host/ehci-msm.c
View file

@ -9,6 +9,7 @@
#include <common.h>
#include <dm.h>
#include <dm/lists.h>
#include <errno.h>
#include <usb.h>
#include <usb/ehci-ci.h>
@ -119,6 +120,24 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
return 0;
}
static int ehci_usb_of_bind(struct udevice *dev)
{
ofnode ulpi_node = ofnode_first_subnode(dev_ofnode(dev));
ofnode phy_node;
if (!ofnode_valid(ulpi_node))
return 0;
phy_node = ofnode_first_subnode(ulpi_node);
if (!ofnode_valid(phy_node)) {
printf("%s: ulpi subnode with no phy\n", __func__);
return -ENOENT;
}
return device_bind_driver_to_node(dev, "msm8916_usbphy", "msm8916_usbphy",
phy_node, NULL);
}
#if defined(CONFIG_CI_UDC)
/* Little quirk that MSM needs with Chipidea controller
* Must reinit phy after reset
@ -132,7 +151,7 @@ void ci_init_after_reset(struct ehci_ctrl *ctrl)
#endif
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "qcom,ehci-host", },
{ .compatible = "qcom,ci-hdrc", },
{ }
};
@ -141,6 +160,7 @@ U_BOOT_DRIVER(usb_ehci) = {
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
.of_to_plat = ehci_usb_of_to_plat,
.bind = ehci_usb_of_bind,
.probe = ehci_usb_probe,
.remove = ehci_usb_remove,
.ops = &ehci_usb_ops,

20
include/configs/dragonboard845c.h
View file

@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#ifndef __CONFIGS_SDM845_H
#define __CONFIGS_SDM845_H
#include <linux/sizes.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
"bootm_low=0x80000000\0" \
"bootcmd=bootm $prevbl_initrd_start_addr\0"
#endif

21
include/configs/qcom.h Normal file
View file

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for Qualcomm Snapdragon boards
*
* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
* (C) Copyright 2023 Linaro Ltd.
*/
#ifndef __CONFIGS_SNAPDRAGON_H
#define __CONFIGS_SNAPDRAGON_H
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
/* Load addressed are calculated during board_late_init(). See arm/mach-snapdragon/board.c */
#define CFG_EXTRA_ENV_SETTINGS \
"stdin=serial,button-kbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"bootcmd=bootm $prevbl_initrd_start_addr\0"
#endif

20
include/configs/qcs404-evb.h
View file

@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for QCS404 evaluation board
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#ifndef __CONFIGS_QCS404EVB_H
#define __CONFIGS_QCS404EVB_H
#include <linux/sizes.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
"bootm_low=0x80000000\0" \
"bootcmd=bootm $prevbl_initrd_start_addr\0"
#endif

26
include/configs/sdm845.h
View file

@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for boards, based on Qualcomm SDM845 chip
*
* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
*/
#ifndef __CONFIGS_SDM845_H
#define __CONFIGS_SDM845_H
#include <linux/sizes.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x4000000\0" \
"bootm_low=0x80000000\0" \
"stdin=serial,button-kbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
"bootcmd=source $prevbl_initrd_start_addr:bootscript\0"
/* Size of malloc() pool */
#endif

37
include/dt-bindings/arm/coresight-cti-dt.h Normal file
View file

@ -0,0 +1,37 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for the defined trigger signal
* types on CoreSight CTI.
*/
#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
#define GEN_IO 0
#define GEN_INTREQ 1
#define GEN_INTACK 2
#define GEN_HALTREQ 3
#define GEN_RESTARTREQ 4
#define PE_EDBGREQ 5
#define PE_DBGRESTART 6
#define PE_CTIIRQ 7
#define PE_PMUIRQ 8
#define PE_DBGTRIGGER 9
#define ETM_EXTOUT 10
#define ETM_EXTIN 11
#define SNK_FULL 12
#define SNK_ACQCOMP 13
#define SNK_FLUSHCOMP 14
#define SNK_FLUSHIN 15
#define SNK_TRIGIN 16
#define STM_ASYNCOUT 17
#define STM_TOUT_SPTE 18
#define STM_TOUT_SW 19
#define STM_TOUT_HETE 20
#define STM_HWEVENT 21
#define ELA_TSTART 22
#define ELA_TSTOP 23
#define ELA_DBGREQ 24
#define CTI_TRIG_MAX 25
#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */

116
include/dt-bindings/clock/qcom,camcc-sdm845.h Normal file
View file

@ -0,0 +1,116 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
/* CAM_CC clock registers */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_AREG_CLK 1
#define CAM_CC_BPS_AXI_CLK 2
#define CAM_CC_BPS_CLK 3
#define CAM_CC_BPS_CLK_SRC 4
#define CAM_CC_CAMNOC_ATB_CLK 5
#define CAM_CC_CAMNOC_AXI_CLK 6
#define CAM_CC_CCI_CLK 7
#define CAM_CC_CCI_CLK_SRC 8
#define CAM_CC_CPAS_AHB_CLK 9
#define CAM_CC_CPHY_RX_CLK_SRC 10
#define CAM_CC_CSI0PHYTIMER_CLK 11
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
#define CAM_CC_CSI1PHYTIMER_CLK 13
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
#define CAM_CC_CSI2PHYTIMER_CLK 15
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
#define CAM_CC_CSI3PHYTIMER_CLK 17
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
#define CAM_CC_CSIPHY0_CLK 19
#define CAM_CC_CSIPHY1_CLK 20
#define CAM_CC_CSIPHY2_CLK 21
#define CAM_CC_CSIPHY3_CLK 22
#define CAM_CC_FAST_AHB_CLK_SRC 23
#define CAM_CC_FD_CORE_CLK 24
#define CAM_CC_FD_CORE_CLK_SRC 25
#define CAM_CC_FD_CORE_UAR_CLK 26
#define CAM_CC_ICP_APB_CLK 27
#define CAM_CC_ICP_ATB_CLK 28
#define CAM_CC_ICP_CLK 29
#define CAM_CC_ICP_CLK_SRC 30
#define CAM_CC_ICP_CTI_CLK 31
#define CAM_CC_ICP_TS_CLK 32
#define CAM_CC_IFE_0_AXI_CLK 33
#define CAM_CC_IFE_0_CLK 34
#define CAM_CC_IFE_0_CLK_SRC 35
#define CAM_CC_IFE_0_CPHY_RX_CLK 36
#define CAM_CC_IFE_0_CSID_CLK 37
#define CAM_CC_IFE_0_CSID_CLK_SRC 38
#define CAM_CC_IFE_0_DSP_CLK 39
#define CAM_CC_IFE_1_AXI_CLK 40
#define CAM_CC_IFE_1_CLK 41
#define CAM_CC_IFE_1_CLK_SRC 42
#define CAM_CC_IFE_1_CPHY_RX_CLK 43
#define CAM_CC_IFE_1_CSID_CLK 44
#define CAM_CC_IFE_1_CSID_CLK_SRC 45
#define CAM_CC_IFE_1_DSP_CLK 46
#define CAM_CC_IFE_LITE_CLK 47
#define CAM_CC_IFE_LITE_CLK_SRC 48
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
#define CAM_CC_IFE_LITE_CSID_CLK 50
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
#define CAM_CC_IPE_0_AHB_CLK 52
#define CAM_CC_IPE_0_AREG_CLK 53
#define CAM_CC_IPE_0_AXI_CLK 54
#define CAM_CC_IPE_0_CLK 55
#define CAM_CC_IPE_0_CLK_SRC 56
#define CAM_CC_IPE_1_AHB_CLK 57
#define CAM_CC_IPE_1_AREG_CLK 58
#define CAM_CC_IPE_1_AXI_CLK 59
#define CAM_CC_IPE_1_CLK 60
#define CAM_CC_IPE_1_CLK_SRC 61
#define CAM_CC_JPEG_CLK 62
#define CAM_CC_JPEG_CLK_SRC 63
#define CAM_CC_LRME_CLK 64
#define CAM_CC_LRME_CLK_SRC 65
#define CAM_CC_MCLK0_CLK 66
#define CAM_CC_MCLK0_CLK_SRC 67
#define CAM_CC_MCLK1_CLK 68
#define CAM_CC_MCLK1_CLK_SRC 69
#define CAM_CC_MCLK2_CLK 70
#define CAM_CC_MCLK2_CLK_SRC 71
#define CAM_CC_MCLK3_CLK 72
#define CAM_CC_MCLK3_CLK_SRC 73
#define CAM_CC_PLL0 74
#define CAM_CC_PLL0_OUT_EVEN 75
#define CAM_CC_PLL1 76
#define CAM_CC_PLL1_OUT_EVEN 77
#define CAM_CC_PLL2 78
#define CAM_CC_PLL2_OUT_EVEN 79
#define CAM_CC_PLL3 80
#define CAM_CC_PLL3_OUT_EVEN 81
#define CAM_CC_SLOW_AHB_CLK_SRC 82
#define CAM_CC_SOC_AHB_CLK 83
#define CAM_CC_SYS_TMR_CLK 84
/* CAM_CC Resets */
#define TITAN_CAM_CC_CCI_BCR 0
#define TITAN_CAM_CC_CPAS_BCR 1
#define TITAN_CAM_CC_CSI0PHY_BCR 2
#define TITAN_CAM_CC_CSI1PHY_BCR 3
#define TITAN_CAM_CC_CSI2PHY_BCR 4
#define TITAN_CAM_CC_MCLK0_BCR 5
#define TITAN_CAM_CC_MCLK1_BCR 6
#define TITAN_CAM_CC_MCLK2_BCR 7
#define TITAN_CAM_CC_MCLK3_BCR 8
#define TITAN_CAM_CC_TITAN_TOP_BCR 9
/* CAM_CC GDSCRs */
#define BPS_GDSC 0
#define IPE_0_GDSC 1
#define IPE_1_GDSC 2
#define IFE_0_GDSC 3
#define IFE_1_GDSC 4
#define TITAN_TOP_GDSC 5
#endif

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