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https://github.com/ARM-software/arm-trusted-firmware.git
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ed6d4a3b48
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Note: cortex_a510.S is applicable and being used only by arm_fpga platform.
However, to test the ported changes, below steps were carried out on the
fvp and the obtained results has been verified.
Testing was conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata.
* Testing via script was not complete, as it directed to verify the
check and the workaround functions of few erratas manually.
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Manual comparison of disassembly of both both files(bl31.elf)
ensured, the ported changes were identical and hence verified.
* Build for release with all errata flags enabled and run default
tftf tests.
CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp \
ARCH=aarch64 \
DEBUG=0 \
HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 \
CTX_INCLUDE_AARCH32_REGS=0 \
ERRATA_A510_1922240=1 \
ERRATA_A510_2288014=1 \
ERRATA_A510_2042739=1 \
ERRATA_A510_2041909=1 \
ERRATA_A510_2250311=1 \
ERRATA_A510_2218950=1 \
ERRATA_A510_2172148=1 \
ERRATA_A510_2347730=1 \
ERRATA_A510_2371937=1 \
ERRATA_A510_2666669=1 \
ERRATA_A510_2684597=1 \
ERRATA_DSU_2313941=1 \
BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
fip all -j12
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure that if Errata are applicable then the
workaround functions are entered precisely.
Change-Id: Icf7aa25c0b3b30f5e2ad6db83953f7f4f0b201d9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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|---|---|---|
| .. | ||
| a64fx.S | ||
| aem_generic.S | ||
| cortex_a35.S | ||
| cortex_a53.S | ||
| cortex_a55.S | ||
| cortex_a57.S | ||
| cortex_a65.S | ||
| cortex_a65ae.S | ||
| cortex_a72.S | ||
| cortex_a73.S | ||
| cortex_a75.S | ||
| cortex_a75_pubsub.c | ||
| cortex_a76.S | ||
| cortex_a76ae.S | ||
| cortex_a77.S | ||
| cortex_a78.S | ||
| cortex_a78_ae.S | ||
| cortex_a78c.S | ||
| cortex_a510.S | ||
| cortex_a520.S | ||
| cortex_a710.S | ||
| cortex_a715.S | ||
| cortex_a720.S | ||
| cortex_blackhawk.S | ||
| cortex_chaberton.S | ||
| cortex_x1.S | ||
| cortex_x2.S | ||
| cortex_x3.S | ||
| cortex_x4.S | ||
| cpu_helpers.S | ||
| cpuamu.c | ||
| cpuamu_helpers.S | ||
| denver.S | ||
| dsu_helpers.S | ||
| generic.S | ||
| neoverse_e1.S | ||
| neoverse_hermes.S | ||
| neoverse_n1.S | ||
| neoverse_n1_pubsub.c | ||
| neoverse_n2.S | ||
| neoverse_n_common.S | ||
| neoverse_poseidon.S | ||
| neoverse_v1.S | ||
| neoverse_v2.S | ||
| qemu_max.S | ||
| rainier.S | ||
| wa_cve_2017_5715_bpiall.S | ||
| wa_cve_2017_5715_mmu.S | ||
| wa_cve_2022_23960_bhb.S | ||
| wa_cve_2022_23960_bhb_vector.S | ||