Jit Loon Lim ddaf02d171 feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA ... This patch is used to implement sdmmc/nand/combo-phy driver to support Cadence IP for Agilex5 SoC FPGA. 1. Added SDMMC/NAND/COMBO-PHY support. 2. Updated product name -> Agilex5 3. Updated QSPI base address Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6		2023-07-05 10:11:11 +08:00
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arch	refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init	2023-06-29 09:59:06 +01:00
bl1	style: remove useless trailing semicolon and line continuations	2023-03-09 14:59:08 +01:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	fix(tree): correct some typos	2023-05-09 15:57:12 +01:00
bl32	refactor(libc): clean up dependencies in libc	2022-09-22 13:23:49 +02:00
common	refactor(fdt-wrappers): fix for unit testing errors	2023-06-26 15:03:08 -05:00
drivers	feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA	2023-07-05 10:11:11 +08:00
dt-bindings	feat(dt-bindings): add TZC400 bindings for STM32MP13	2022-03-22 09:09:23 +01:00
export	fix: integer suffix macro definition	2023-06-20 15:22:19 +02:00
lib	Merge changes from topic "gr/cpu_rename" into integration	2023-06-29 17:36:44 +02:00
plat	fix(fvp): adjust BL31 maximum size as per total SRAM size	2023-06-28 21:53:51 +01:00
services	chore: remove unused and undefined function	2023-06-06 08:19:06 -07:00
tools_share	feat(cert-create): add new option for CCA NV ctr	2023-05-25 16:40:43 -05:00