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style: remove useless trailing semicolon and line continuations

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found using checkpatch.pl[1]

[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c
This commit is contained in:
Elyes Haouas 2023-02-13 10:05:41 +01:00 • committed by Elyes HAOUAS
parent 1fc7106ce1
commit 9a90d720b8
24 changed files with 48 additions and 48 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
bl1/bl1_fwu.c
View file

@ -420,7 +420,7 @@ static int bl1_fwu_image_auth(unsigned int image_id,
* Image is in RESET state.
* Check the parameters and authenticate the source image in place.
*/
if (bl1_plat_mem_check(image_src, image_size, \
if (bl1_plat_mem_check(image_src, image_size,
desc->ep_info.h.attr) != 0) {
WARN("BL1-FWU: Authentication arguments source/size not mapped\n");
return -ENOMEM;

2
drivers/auth/mbedtls/mbedtls_x509_parser.c
View file

@ -474,5 +474,5 @@ static int get_auth_param(const auth_param_type_desc_t *type_desc,
return rc;
}
REGISTER_IMG_PARSER_LIB(IMG_CERT, LIB_NAME, init, \
REGISTER_IMG_PARSER_LIB(IMG_CERT, LIB_NAME, init,
check_integrity, get_auth_param);

16
include/arch/aarch32/smccc_helpers.h
View file

@ -90,21 +90,21 @@ typedef struct smc_ctx {
* ensure that the assembler and the compiler view of the offsets of
* the structure members is the same.
*/
CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \
CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0),
assert_smc_ctx_greg_r0_offset_mismatch);
CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \
CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1),
assert_smc_ctx_greg_r1_offset_mismatch);
CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \
CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2),
assert_smc_ctx_greg_r2_offset_mismatch);
CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \
CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3),
assert_smc_ctx_greg_r3_offset_mismatch);
CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \
CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4),
assert_smc_ctx_greg_r4_offset_mismatch);
CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \
CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr),
assert_smc_ctx_sp_usr_offset_mismatch);
CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \
CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon),
assert_smc_ctx_lr_mon_offset_mismatch);
CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \
CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon),
assert_smc_ctx_spsr_mon_offset_mismatch);
CASSERT((sizeof(smc_ctx_t) & 0x7U) == 0U, assert_smc_ctx_not_aligned);

2
include/arch/aarch64/arch_helpers.h
View file

@ -692,7 +692,7 @@ void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
isb(); \
}
#else
#define AT(_at_inst, _va) _at_inst(_va);
#define AT(_at_inst, _va) _at_inst(_va)
#endif
#endif /* ARCH_HELPERS_H */

4
include/bl1/bl1.h
View file

@ -90,8 +90,8 @@ void bl1_plat_prepare_exit(entry_point_info_t *ep_info);
/*
* Check if the total number of FWU SMC calls are as expected.
*/
CASSERT(FWU_NUM_SMC_CALLS == \
(FWU_SMC_FID_END - FWU_SMC_FID_START + 1),\
CASSERT(FWU_NUM_SMC_CALLS ==
(FWU_SMC_FID_END - FWU_SMC_FID_START + 1),
assert_FWU_NUM_SMC_CALLS_mismatch);
/* Utility functions */

6
include/common/runtime_svc.h
View file

@ -90,11 +90,11 @@ typedef struct rt_svc_desc {
* 3. ensure that the assembler and the compiler see the handler
* routine at the same offset.
*/
CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC), \
CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC),
assert_sizeof_rt_svc_desc_mismatch);
CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init), \
CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init),
assert_rt_svc_desc_init_offset_mismatch);
CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \
CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle),
assert_rt_svc_desc_handle_offset_mismatch);

2
include/lib/el3_runtime/aarch32/context.h
View file

@ -62,7 +62,7 @@ typedef struct cpu_context {
* ensure that the assembler and the compiler view of the offsets of
* the structure members is the same.
*/
CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \
CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx),
assert_core_context_regs_offset_mismatch);
#endif /* __ASSEMBLER__ */

14
include/lib/el3_runtime/aarch64/context.h
View file

@ -445,24 +445,24 @@ typedef struct cpu_context {
* ensure that the assembler and the compiler view of the offsets of
* the structure members is the same.
*/
CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx),
assert_core_context_gp_offset_mismatch);
CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \
CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx),
assert_core_context_el1_sys_offset_mismatch);
#if CTX_INCLUDE_EL2_REGS
CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \
CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx),
assert_core_context_el2_sys_offset_mismatch);
#endif
#if CTX_INCLUDE_FPREGS
CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx),
assert_core_context_fp_offset_mismatch);
#endif
CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx),
assert_core_context_el3state_offset_mismatch);
CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \
CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx),
assert_core_context_cve_2018_3639_offset_mismatch);
#if CTX_INCLUDE_PAUTH_REGS
CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \
CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx),
assert_core_context_pauth_offset_mismatch);
#endif

2
lib/locks/bakery/bakery_lock_normal.c
View file

@ -44,7 +44,7 @@
* Using this value, if provided, rather than the linker generated value results in
* more efficient code
*/
CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0,
PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple);
#define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE)
#else

4
lib/xlat_tables/aarch32/nonlpae_tables.c
View file

@ -518,9 +518,9 @@ void enable_mmu_svc_mon(unsigned int flags)
/* Enable Access flag (simplified access permissions) and TEX remap */
write_sctlr(read_sctlr() | SCTLR_AFE_BIT | SCTLR_TRE_BIT);
prrr = MMU32B_PRRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 1, 0) \
prrr = MMU32B_PRRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 1, 0)
| MMU32B_PRRR_IDX(MMU32B_ATTR_IWBWA_OWBWA_INDEX, 2, 1);
nmrr = MMU32B_NMRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 0, 0) \
nmrr = MMU32B_NMRR_IDX(MMU32B_ATTR_DEVICE_INDEX, 0, 0)
| MMU32B_NMRR_IDX(MMU32B_ATTR_IWBWA_OWBWA_INDEX, 1, 1);
prrr |= MMU32B_PRRR_NS1 | MMU32B_PRRR_DS1;

4
plat/arm/board/fvp/fvp_common.c
View file

@ -180,8 +180,8 @@ const mmap_region_t plat_arm_mmap[] = {
#if defined(IMAGE_BL31) && SPM_MM
const mmap_region_t plat_arm_secure_partition_mmap[] = {
V2M_MAP_IOFPGA_EL0, /* for the UART */
MAP_REGION_FLAT(DEVICE0_BASE, \
DEVICE0_SIZE, \
MAP_REGION_FLAT(DEVICE0_BASE,
DEVICE0_SIZE,
MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,

8
plat/arm/board/fvp_r/fvp_r_bl1_setup.c
View file

@ -109,10 +109,10 @@ void arm_bl1_plat_arch_setup(void)
ARM_MAP_BL_COHERENT_RAM,
#endif
/* DRAM1_region: */
MAP_REGION_FLAT( \
PLAT_ARM_DRAM1_BASE, \
PLAT_ARM_DRAM1_SIZE, \
MT_MEMORY | MT_SECURE | MT_EXECUTE \
MAP_REGION_FLAT(
PLAT_ARM_DRAM1_BASE,
PLAT_ARM_DRAM1_SIZE,
MT_MEMORY | MT_SECURE | MT_EXECUTE
| MT_RW | MT_NON_CACHEABLE),
/* NULL terminator: */
{0}

2
plat/arm/board/rde1edge/rde1edge_topology.c
View file

@ -31,6 +31,6 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
};

2
plat/arm/common/aarch64/arm_sdei.c
View file

@ -38,7 +38,7 @@ void plat_sdei_setup(void)
}
for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_cnt); i++) {
arm_sdei_shared[i] = (sdei_ev_map_t)SDEI_SHARED_EVENT( \
arm_sdei_shared[i] = (sdei_ev_map_t)SDEI_SHARED_EVENT(
FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_nums[i]),
FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_intrs[i]),
FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_flags[i]));

2
plat/arm/common/arm_pm.c
View file

@ -191,7 +191,7 @@ void plat_arm_program_trusted_mailbox(uintptr_t address)
* ARM_SHARED_RAM region.
*/
assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <=
(ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
}

2
plat/nvidia/tegra/drivers/flowctrl/flowctrl.c
View file

@ -84,7 +84,7 @@ static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr)
void tegra_fc_ccplex_pgexit_lock(void)
{
unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;;
uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;
uint32_t icept_cpu_flags[] = {
INTERCEPT_EXIT_PG_CORE0,
INTERCEPT_EXIT_PG_CORE1,

2
plat/nvidia/tegra/drivers/pmc/pmc.c
View file

@ -103,7 +103,7 @@ void tegra_pmc_lock_cpu_vectors(void)
bool tegra_pmc_is_last_on_cpu(void)
{
int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);;
uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
bool status = true;
/* check if this is the last standing CPU */

4
plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
View file

@ -372,8 +372,8 @@ int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
* StandbyWFI or the equivalent signal, and always keeping the IDLE
* voltage/frequency request register enabled.
*/
val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |
((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
return ari_request_wait(ari_base, 0U,

4
plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
View file

@ -246,8 +246,8 @@ int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
* StandbyWFI or the equivalent signal, and always keeping the IDLE
* voltage/frequency request register enabled.
*/
val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |
((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);

2
plat/nvidia/tegra/soc/t194/plat_smmu.c
View file

@ -24,7 +24,7 @@ static uint32_t tegra_misc_read_32(uint32_t off)
uint32_t plat_get_num_smmu_devices(void)
{
uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >>
BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
if (board_revid == BOARD_SYSTEM_FPGA_BASE) {

2
plat/rockchip/rk3399/drivers/dp/cdn_dp.h
View file

@ -34,7 +34,7 @@ struct cdn_dp_hdcp_key_1x {
#define HDCP_KEY_1X_STORE_DATA_ALIGN_SIZE (6 * 64) / 8
/* Checks the cdn_dp_hdcp_key_1x must be aligned on 6 x 64-bit word boundary */
CASSERT(sizeof(struct cdn_dp_hdcp_key_1x) % HDCP_KEY_1X_STORE_DATA_ALIGN_SIZE, \
CASSERT(sizeof(struct cdn_dp_hdcp_key_1x) % HDCP_KEY_1X_STORE_DATA_ALIGN_SIZE,
assert_hdcp_key_1x_store_data_align_size_mismatch);
uint64_t dp_hdcp_ctrl(uint64_t type);

2
services/spd/opteed/opteed_private.h
View file

@ -114,7 +114,7 @@ DEFINE_REG_STRUCT(c_rt_regs, OPTEED_C_RT_CTX_ENTRIES);
* have the same double word aligned view of the size of the C runtime
* register context.
*/
CASSERT(OPTEED_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \
CASSERT(OPTEED_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),
assert_spd_c_rt_regs_size_mismatch);
/*******************************************************************************

2
services/spd/tlkd/tlkd_private.h
View file

@ -85,7 +85,7 @@ DEFINE_REG_STRUCT(c_rt_regs, TLKD_C_RT_CTX_ENTRIES);
* have the same double word aligned view of the size of the C runtime
* register context.
*/
CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \
CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),
assert_tlkd_c_rt_regs_size_mismatch);
/*******************************************************************************

4
services/spd/tspd/tspd_private.h
View file

@ -146,7 +146,7 @@ DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES);
* have the same double word aligned view of the size of the C runtime
* register context.
*/
CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \
CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),
assert_spd_c_rt_regs_size_mismatch);
/* SEL1 Secure payload (SP) caller saved register context structure. */
@ -157,7 +157,7 @@ DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES);
* have the same double word aligned view of the size of the C runtime
* register context.
*/
CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \
CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t),
assert_spd_sp_regs_size_mismatch);
/*******************************************************************************