Sieu Mun Tang ce21a1a909 feat(intel): update Agilex5 DDR and IOSSM driver ... DDR and IOSSM driver code for Agilex5 platform, initialize the DDR/IOSSM in BL2 EL3 early flow. Change-Id: I3e4205171d9356190b60498cae322318520bb1c2 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>		2024-10-07 17:28:30 +02:00
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plat_macros.S	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
platform_def.h	feat(intel): enable query of fip offset on RSU	2024-01-16 13:26:35 +08:00
socfpga_emac.h	intel: Enable EMAC PHY in Intel FPGA platform	2020-02-25 10:19:51 +08:00
socfpga_f2sdram_manager.h	feat(intel): reset manager support for Agilex5 SoC FPGA	2023-07-05 09:08:31 +08:00
socfpga_fcs.h	fix(intel): update checking for memcpy and memset	2023-05-23 21:09:01 +08:00
socfpga_handoff.h	feat(intel): update Agilex5 DDR and IOSSM driver	2024-10-07 17:28:30 +02:00
socfpga_mailbox.h	feat(intel): add QSPI get devinfo mailbox cmd	2024-04-16 22:17:00 +08:00
socfpga_noc.h	feat(intel): platform enablement for Agilex5 SoC FPGA	2023-07-05 10:11:22 +08:00
socfpga_private.h	feat(intel): enable query of fip offset on RSU	2024-01-16 13:26:35 +08:00
socfpga_reset_manager.h	fix(intel): update HPS bridges for Agilex5 SoC FPGA	2023-11-03 21:18:51 +08:00
socfpga_ros.h	feat(intel): support query of fip offset using RSU	2024-01-16 13:26:21 +08:00
socfpga_sip_svc.h	feat(intel): add QSPI get devinfo mailbox cmd	2024-04-16 22:17:00 +08:00
socfpga_system_manager.h	feat(intel): add in QSPI ECC for Linux	2023-12-22 00:39:55 +08:00
socfpga_vab.h	feat(intel): enable VAB support for Intel products	2024-07-21 10:35:17 +08:00