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feat(intel): enable query of fip offset on RSU

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Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform

Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
This commit is contained in:
Mahesh Rao 2023-08-22 17:26:23 +08:00 • committed by Sieu Mun Tang
parent 62be2a1ae3
commit 6cbe2c5d19
8 changed files with 27 additions and 15 deletions
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9
plat/intel/soc/agilex/bl2_plat_setup.c
View file

@ -28,6 +28,7 @@
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
#include "socfpga_reset_manager.h"
#include "socfpga_ros.h"
#include "socfpga_system_manager.h"
#include "wdt/watchdog.h"
@ -92,6 +93,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
void bl2_el3_plat_arch_setup(void)
{
unsigned long offset = 0;
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
@ -123,14 +125,17 @@ void bl2_el3_plat_arch_setup(void)
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
dw_mmc_init(&params, &mmc_info);
socfpga_io_setup(boot_source);
socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
break;
case BOOT_SOURCE_QSPI:
cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
socfpga_io_setup(boot_source);
if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) {
offset = PLAT_QSPI_DATA_BASE;
}
socfpga_io_setup(boot_source, offset);
break;
default:

1
plat/intel/soc/agilex/platform.mk
View file

@ -47,6 +47,7 @@ BL2_SOURCES += \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_ros.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \
plat/intel/soc/common/soc/socfpga_firewall.c \

11
plat/intel/soc/agilex5/bl2_plat_setup.c
View file

@ -34,6 +34,7 @@
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
#include "socfpga_reset_manager.h"
#include "socfpga_ros.h"
#include "wdt/watchdog.h"
@ -96,6 +97,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
void bl2_el3_plat_arch_setup(void)
{
handoff reverse_handoff_ptr;
unsigned long offset = 0;
struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk());
@ -109,7 +111,7 @@ void bl2_el3_plat_arch_setup(void)
case BOOT_SOURCE_SDMMC:
NOTICE("SDMMC boot\n");
sdmmc_init(&reverse_handoff_ptr, &params, &mmc_info);
socfpga_io_setup(boot_source);
socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
break;
case BOOT_SOURCE_QSPI:
@ -117,13 +119,16 @@ void bl2_el3_plat_arch_setup(void)
cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
socfpga_io_setup(boot_source);
if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) {
offset = PLAT_QSPI_DATA_BASE;
}
socfpga_io_setup(boot_source, offset);
break;
case BOOT_SOURCE_NAND:
NOTICE("NAND boot\n");
nand_init(&reverse_handoff_ptr);
socfpga_io_setup(boot_source);
socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE);
break;
default:

1
plat/intel/soc/agilex5/platform.mk
View file

@ -60,6 +60,7 @@ BL2_SOURCES += \
plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_ros.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/socfpga_vab.c \
plat/intel/soc/common/soc/socfpga_emac.c \

4
plat/intel/soc/common/include/platform_def.h
View file

@ -44,6 +44,10 @@
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#endif
#define PLAT_QSPI_DATA_BASE (0x3C00000)
#define PLAT_NAND_DATA_BASE (0x0200000)
#define PLAT_SDMMC_DATA_BASE (0x0)
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/

2
plat/intel/soc/common/include/socfpga_private.h
View file

@ -33,7 +33,7 @@ typedef enum {
void enable_nonsecure_access(void);
void socfpga_io_setup(int boot_source);
void socfpga_io_setup(int boot_source, unsigned long offset);
void socfgpa_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,

10
plat/intel/soc/common/socfpga_storage.c
View file

@ -24,16 +24,13 @@
#include "drivers/sdmmc/sdmmc.h"
#include "socfpga_private.h"
#include "socfpga_ros.h"
#define PLAT_FIP_BASE (0)
#define PLAT_FIP_MAX_SIZE (0x1000000)
#define PLAT_MMC_DATA_BASE (0xffe3c000)
#define PLAT_MMC_DATA_SIZE (0x2000)
#define PLAT_QSPI_DATA_BASE (0x3C00000)
#define PLAT_QSPI_DATA_SIZE (0x1000000)
#define PLAT_NAND_DATA_BASE (0x0200000)
#define PLAT_NAND_DATA_SIZE (0x1000000)
static const io_dev_connector_t *fip_dev_con;
static const io_dev_connector_t *boot_dev_con;
@ -136,9 +133,10 @@ static int check_fip(const uintptr_t spec)
return result;
}
void socfpga_io_setup(int boot_source)
void socfpga_io_setup(int boot_source, unsigned long offset)
{
int result;
fip_spec.offset = offset;
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
@ -152,7 +150,6 @@ void socfpga_io_setup(int boot_source)
case BOOT_SOURCE_QSPI:
register_io_dev = &register_io_dev_memmap;
fip_spec.offset = PLAT_QSPI_DATA_BASE;
break;
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
@ -161,7 +158,6 @@ void socfpga_io_setup(int boot_source)
nand_dev_spec.ops.init = cdns_nand_init_mtd;
nand_dev_spec.ops.read = cdns_nand_read;
nand_dev_spec.ops.write = NULL;
fip_spec.offset = PLAT_NAND_DATA_BASE;
break;
#endif

4
plat/intel/soc/stratix10/bl2_plat_setup.c
View file

@ -122,14 +122,14 @@ void bl2_el3_plat_arch_setup(void)
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
dw_mmc_init(&params, &mmc_info);
socfpga_io_setup(boot_source);
socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
break;
case BOOT_SOURCE_QSPI:
cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
socfpga_io_setup(boot_source);
socfpga_io_setup(boot_source, PLAT_QSPI_DATA_BASE);
break;
default: